AT697F_14 datasheet(41/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

Each unit n is configured by two write protection registers (WPSTAn and WPSTOn):

•

the unit can be enabled/disabled(1) in supervisor mode(2) (WPSTOn.su) and in user

mode(3) (WPSTOn.us)

•

the segment is defined by a START address(4) (WPSTAn.start) and an END

address(4) (WPSTOn.end)

•

protection can be performed inside/outside the segment (WPSTAn.bp)

Notes: 1. The unit is enabled as soon as one of the two modes is enabled

2. The DSU communication interface has supervisor status when accessing the RAM

area

3. The PCI interface (DMA and Target) has user status when accessing the RAM area

4. Address is a 32-bit word-aligned offset from the start of the RAM area (0x40000000)

Figure 19. Start/End Address Scheme Protection Overview

Segment mode (

bp = 0)

Block mode (

bp = 1)

RAM

Write

trap

Write

trap

Write

trap

Block

Protected

Allowed

Segment

END

START

END

START

The protection is based on a segment of any arbitrary size in the RAM address space

(4 bytes to 1 GB):

Table 11. Write Address Comparison

field

Most significant write address bits

word

The most significant bits of the write address are simply compared against the START

and the END address of the segment (both boundaries included) to determine if the

write address is inside the defined segment or in the block (outside of this segment).

If the write protection unit is enabled for the current IU mode (user or supervisor) and a

block or segment protection error is detected, the write access is cancelled and a

write_error trap (0x2B) is generated.

Tag/Mask Address Scheme

Tag/Mask address scheme protection is implemented as two write protection units

capable of each controlling write access inside/outside of a binary aligned memory seg-

ment in the range of 32 KB - 1 GB.

bit num

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210

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