AT697F_14 datasheet(39/176 Pages) ATMEL

39 / 176 page

AT697F

7703E–AERO–08/11

SDRAM devices shall be 64 Mbit, 256 Mbit or 512 Mbit with 8 to 12 column-address bits,

up to 13 row-address bits and exclusively 4 internal data banks. Only 32-bit data bus

width is supported.

The SDRAMs address bus shall be connected to A[14:2] and the bank address to

A[16:15]. Devices with less than 13 address pins should only use the less significant

bits of A[14:2].

SDRAM banks map as follows:

•

SDCS*[0] and SDCS*[1] decode 2 contiguous banks with a common

programmable size (4 MB to 512 MB)

•

SDCS*[1:0] decode the upper half of the RAM area (0x60000000 -

0x7FFFFFFF) when the SRAM interface is enabled

•

SDCS*[1:0] decode the lower half of the RAM area (0x40000000 - 0x5FFFFFFF)

when the SRAM interface is disabled

The SDRAM interface is controlled in the memory configuration registers (MCFG2 and

MCFG3):

•

interface can be enabled/disabled (MCFG2.se)

•

bank size can be set from 4 MB to 512 MB (MCFG2.sdrbs)

•

column size can be set from 256 to 4096 (MCFG2.sdrcls)

•

commands can be sent to the devices (MCFG2.sdrcmd)

•

timings parameters can be set (MCFG2.sdrcas, MCFG2.trp and MCFG2.trfc)

•

auto-refresh can be enabled/disabled (MCFG2.sdrref) and programmed

(MCFG3.srcrv)

•

EDAC protection(1)(2) can be enabled/disabled (MCFG3.re)

Notes: 1. EDAC protection activation common to SRAM and SDRAM interfaces.

2. Read-modify-write on sub-word operations simultaneously activated with EDAC.

Initialization

After reset, the SDRAM controller automatically performs an SDRAM initialization

sequence. It consists in a PRECHARGE cycle, two AUTO-REFRESH cycles and a LOAD-

MODE-REG cycle on both SDRAM banks simultaneously.

The controller programs the SDRAM to use page burst on read and single location

access on write.

Timing Parameters

The SDRAM interface parameters can be programmed so read/write access to SDRAM

devices is optimized:

Table 10. SDRAM Programmable Timing Parameters

CAS latency, RAS/CAS delay

tCAS, tRCD

2 - 3

clocks

MCFG2.sdrcas

Precharge to activate

tRP

2 - 3

clocks

MCFG2.trp

Auto-refresh command period

tRFC

3 - 11

clocks

MCFG2.trfc

Auto-refresh interval

10 - 32768

clocks

MCFG3.srcrv

Refresh

The SDRAM controller embeds a refresh module. When enabled (MCFG2.sdrref = 1),

it periodically issues an AUTO-REFRESH command to both SDRAM banks with a pro-

grammable period (MCFG3.srcrv).

Function

Parameter

Range

Unit

Control

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