AT697F_14 datasheet(65/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

in Host-Bridge mode (SYSEN* = 0), while they can only be programmed by the

remote host-bridge when in Satellite mode (SYSEN* = 1).

The other PCI target registers (PCITSC & PCITPA) are always and only accessible

by the processor.

2. At least one of target Memory Space (PCISC.com1) and target I/O Space

(PCISC.com0) shall be enabled for target operation

Caution: If the PCI target is to share any data with the processor while the data cache is active

(CCR.dcs = 01 or 11), care shall be taken to first enable the data cache snooper

(CCR.ds = 1) or flush the data cache (CCR.fd = 1) when appropriate.

If the PCI target is to provide any instruction to the processor to execute while the

instruction cache is active (CCR.ics = 01 or 11), care shall be taken to flush the instruc-

tion cache (CCR.fi = 1) when appropriate.

Limitations

The following limitations shall be considered when using the PCI target:

•

The PCI target cannot operate within the PCI memory-mapped address range in

local memory. If the programmed target local address (PCITPA) lies in the PCI

memory-mapped address range (0xA0000000 - 0xFFFFFFFF), the target

controller will cancel the transfer and report an error (PCIITP.tier = 1).

•

Target read transactions assume the target space to be prefetchable (reading from

an address does not alter the data) and target Memory Read and I/O Read

commands are generally prefetched.

The target controller prefetches up to 8 words into the transmit FIFO once the target

read address is available. After the last required data word is transferred to the PCI

interface, the FIFO is automatically flushed to discard any unused prefetched data.

This behavior shall be considered if a non-prefetchable device (like a UART) is to be

read through the PCI target interface.

•

The interface supports the following PCI write byte-enable patterns (C/BE*[3:0]):

single-byte (0111, 1011, 1101 & 1110), half-word (0011 & 1100), word (0000)

and ignore-data (1111, frequently used as a dummy write cycle). A data received

with any other byte-enable pattern is discarded and an error is reported

(PCIITP.tber = 1).

Delayed-Read

As specified in the PCI standard, delayed-read functionality is implemented as follows:

•

When a read request was retried (because data from local memory is not available

yet), the interface remains locked for any other target read (targeting different

addresses). The initiator of the original read is expected to later repeat the request

to the same address.

•

A delayed-read can however be interrupted by one or more PCI write accesses. The

PCI standard requires each write command to be processed first so to prevent a

system lock-up.

•

Meanwhile, the interface prefetches read-data from local memory into the target-

transmit FIFO (TXMT). When the read request is repeated (after the interfering

write, if any), the requested data is available in the FIFO and the delayed-transfer

completes normally.

PCI Error Reporting

Parity check, parity error signal (PERR*) and system error signal (SERR*) are imple-

mented as foreseen by the PCI standard. They can be controlled in the combined PCI

Command & Status register (PCISC).

In addition, PCI initiator and PCI target error conditions and status information are

always reported(1) in PCIITP (PCI Interrupt Pending).

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