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AT697F датащи(PDF) 34 Page - ATMEL Corporation

номер детали AT697F
подробное описание детали  SPARC V8 High Performance Low-power 32-bit Architecture
PDF  176 Pages
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производитель  ATMEL [ATMEL Corporation]
домашняя страница  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT697F датащи(HTML) 34 Page - ATMEL Corporation

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34
AT697F
7703E–AERO–08/11
Read Access
An I/O read access consists in a address lead-in cycle (the IOSEL* signal is delayed by
one clock cycle to provide a stable address for sampling), two data cycles and an
address lead-out-cycle.
Figure 11. I/O Read Access (no wait-states)
lead-in
read
lead-out
SDCLK
A
Address
IOS*
OE*
D
Data
Write Access
An I/O write access consists in an address lead-in cycle, a data write cycle and an
address lead-out cycle. The write operation is strobed by the WRITE* signal.
Figure 12. I/O Write Access (no wait-states)
lead-in
write
lead-out
SDCLK
A
Address
IOS*
WRITE*
D
Data
Wait-States
For application accessing slow I/O devices, the memory controller allows to insert wait-
states during an I/O read /write access (MCFG1.iows). Up to 15 wait-states can be
inserted.
An I/O read/write access can further be stretched when even more delay is needed (see
"BRDY*-Controlled Access" later in this chapter").
Data Bus Width
When configured for 32-bit I/O (MCFG1.iowdh = 00), D[31:0] shall be connected to
the I/O device(s). Only 32-bit load/store instructions (LD, ST) shall be used then.



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