AT697F_14 datasheet(80/176 Pages) ATMEL

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AT697F

7703E–AERO–08/11

PLL

The CPU clock can be issued from the internal PLL.

Overview

The PLL contains a phase/frequency detector, charge pump, voltage control oscillator,

low-pass filter, lock detector and divider.

Figure 49. PLL Block Diagram

Phase/Frequency

Detector

Lock

detector

Charge

Pump

VCO

ckr_int

div_int

lft

BYPASS

CLK

LOCK

Divider

by 4

div

CLKPLL

Internal

filter

The PLL implemented is configured in hardware to provide an internal clock frequency

of four times the frequency of the input clock.

PLL control

The PLL control is performed in hardware through dedicated pins.

The following table presents the assignement and functions of the PLL control pins.

Table 21. PLL Ports Description

LOCK

The PLL is locked and delivers the expected internal clock

CLK

External clock input

BYPASS

Bypass the internal PLL and directly drive the internal clock from CLK

Operation

To drive the device from the internal PLL, the CLK input shall be driven by an external

clock generator while the BYPASS pin is driven low. That way, the CPU clock frequency

is four times the frequency of the clock applied to CLK.

When the PLL is enabled, the CLK clock input shall be driven at a frequency in the range

of 18 MHz up to 25 MHz.

Fault-Tolerance & Clock

To protect against SEU errors (Single Event Upset), each on-chip register is imple-

mented using triple modular redundancy (TMR).

Moreover, an independent clock tree is used for each of the three registers making up

one TMR module. This feature protects against SET errors (Single Event Transient) in

the clock tree, to the expense of increased routing.

The CPU clock and the PCI clock are built as three-clock trees.

Pin name

Function

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