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ICS1531 датащи(PDF) 66 Page - Integrated Circuit Systems

номер детали ICS1531
подробное описание детали  Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
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ICS1531 датащи(HTML) 66 Page - Integrated Circuit Systems

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ICS1531 Rev N 12/1/99
December, 1999
66
Chapter 10
Timing Diagrams
ICS1531 Data Sheet - Preliminary
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
10.2
Power-On Reset Timing
Table 10-2 lists typical ICS1531 power-on reset (POR) timing measures and Figure 10-4 shows the POR
timing relationships. (For information on how the ICS1531 POR circuitry operates, see Section 8.2, “Power
Considerations”.)
If a reset:
• Is desired, reduce the VDD supply voltage (and the voltage on all ICS1531 pins) so that it is below the
threshold voltage (VDDth) of the POR circuit for the period t1. (A time of 10 ms is sufficient.)
• Is not desired, ensure either one or both of the following conditions:
– Ensure the VDD supply voltage (and the voltage on all ICS1531 pins) is not reduced below Vmin.
– If the VDD supply voltage (and the voltage on all ICS1531 pins) is reduced below Vth, then ensure
that it is at this level for less than the period t1.
Note:
The POR signal is an internal signal. It is generated regardless of the ICS1531 mode.
Figure 10-4.
Power-On Reset Condition for ICS1531
Table 10-2.
Typical ICS1531 POR Transition Times
Symbol
Timing Description
Min
Typ
Max
Units
VDD
Supply Voltage (‘On’ State)
3.0
3.3
3.6
V
VDDth
Threshold Supply Voltage
–
1.8
–
V
t1
Hold Time for Reset State
–
10
–
ms
t1
VDDth
VDDmin



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