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ICS1531 датащи(PDF) 38 Page - Integrated Circuit Systems

номер детали ICS1531
подробное описание детали  Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
PDF  76 Pages
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производитель  ICST [Integrated Circuit Systems]
домашняя страница  http://www.icst.com
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ICS1531 датащи(HTML) 38 Page - Integrated Circuit Systems

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ICS1531 Rev N 12/1/99
December, 1999
38
Chapter 6
Register Set
ICS1531 Data Sheet - Preliminary
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
6.5.17
Register 20h: PNLCLK-M
The PNLCLK-M Register is used to divide the reference frequency provided to the PNLCLK PLL. The ‘M’
value is used to determine the output frequency of the PLL as specified in the equation given in Section
6.5.18, “Register 21h: PNLCLK-N”.
6.5.18
Register 21h: PNLCLK-N
The PNLCLK-N Register is used to determine the output frequency of the PNLCLK.
To determine the PNLCLK frequency (which is in units of MHz), use the following equation:
FPNLCLK =
Table 6-17.
PNLCLK-M Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
20:7-
20:0
PNLCLK_M [7-0]
PNLCLK_M (Reference Divider) [7-0].
• This register includes bits for the PNLCLK Reference
Divider.
• The value in this register is used as the variable ‘M’ in the
frequency equation given in Section 6.5.18, “Register
21h: PNLCLK-N”.
R/W
D-PK
0
Table 6-18.
PNLCLK-N Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
21:7-
21:0
PNLCLK_N [7-0]
PNLCLK_N (Feedback Divider) [7-0].
• This register includes bits for the PNLCLK Feedback
Divider.
• The value in this register is used as the variable ‘N’ in the
frequency equation for the PNLCLK.
R/W
D-PK
0
OSC
× (N + 8)
(M + 2)



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