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ICS1531 датащи(PDF) 34 Page - Integrated Circuit Systems

номер детали ICS1531
подробное описание детали  Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator
PDF  76 Pages
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производитель  ICST [Integrated Circuit Systems]
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ICS1531 датащи(HTML) 34 Page - Integrated Circuit Systems

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ICS1531 Rev N 12/1/99
December, 1999
34
Chapter 6
Register Set
ICS1531 Data Sheet - Preliminary
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
6.5.8
Register 07h: OSC Divider
06:2
FUNC_Delay
FUNC Delay.
This bit selects the delay for the ADC_FUNC signal. (See the
note at the first of this table.)
• 0 = The ADC_FUNC signal is delayed by 0 cycles.
• 1 = The ADC_FUNC signal is delayed by 1 cycle, which has
the effect of moving the channel ‘A” data to the ‘B’ channel
output pins and the reverse.
R/W
–
0
06:1-
06:0
Reserved
Reserved.
• See Section 6.1, “Reserved Bits”.
• These bits can be programmed to ‘0’.
––
0
Table 6-11.
OSC Divider Register
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set
07:7-
07:0
OSC_Div [7-0]
Oscillator Divider [7-0].
After the signal from the internal crystal oscillator is divided by
2 (see Figure 4-1), these bits select the value by which the
resulting signal is divided.
• 0 = This divide-down value is reserved.
• 1 = Divide by 1.
• 2 = Divide by 2, and so forth.
R/W
–
0
Table 6-10.
Output Enables Register (Continued)
Bit
Bit Name
Bit Definition
Ac-
cess
Spec.
Func.
Re-
set



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