8

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PS9059A

07/28/12

PI3VDP411LSA

Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)

Table: Differential Input Characteristics forIN_Dx signals

Symbol

Parameter

Min Typ Max Units

Comments

UI, Unit Interval

360

ps

bit rate ranges from 250Mbps to 2.5Gbps per lane.

Nominal Tbit at 2.5 Gbps = 400 ps. 360ps = 400ps-

10%

Input Differential Volt-

age Level

0.175

1.200 V

See note 1 below

Minimum Eye Width at

IN_D input pair

0.8

Tbit

AC Peak Common

Mode Input Voltage

100

mV

See note 2 below

40

50

60

Ω

Required IN_D+ as well as IN_D- DC impedance

(50 ±20% tolerance).

0

2.0

V

Intended to limit power-up stress on chipset's PCIE

output buffers.

100

k Ω

Differential inputs must be in a high impedance

state when OE# is HIGH.

TMDS Outputs

The level shifter's TMDS outputs are required to meet HDMI 1.3 specifications.

The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3

specification.

12-0236