поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

PI3VDP411LSA датащи(PDF) 6 Page - Pericom Semiconductor Corporation

номер детали PI3VDP411LSA
подробное описание детали  Dual Mode DisplayPort to DVI/HDMI Electrical bridge (Level Shifter)
PDF  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  PERICOM [Pericom Semiconductor Corporation]
домашняя страница  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI3VDP411LSA датащи(HTML) 6 Page - Pericom Semiconductor Corporation

Back Button PI3VDP411LSA Datasheet HTML 2Page - Pericom Semiconductor Corporation PI3VDP411LSA Datasheet HTML 3Page - Pericom Semiconductor Corporation PI3VDP411LSA Datasheet HTML 4Page - Pericom Semiconductor Corporation PI3VDP411LSA Datasheet HTML 5Page - Pericom Semiconductor Corporation PI3VDP411LSA Datasheet HTML 6Page - Pericom Semiconductor Corporation PI3VDP411LSA Datasheet HTML 7Page - Pericom Semiconductor Corporation PI3VDP411LSA Datasheet HTML 8Page - Pericom Semiconductor Corporation PI3VDP411LSA Datasheet HTML 9Page - Pericom Semiconductor Corporation PI3VDP411LSA Datasheet HTML 10Page - Pericom Semiconductor Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 13 page
background image
6
www.pericom.com
PS9059A
07/28/12
PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Truth Table (Slew Rate control function)
SR1
SR0
Rise/Fall Time (Typ)
1
1
140ps
1
0
130ps
0
1
120ps
0
0
110ps
Table 1: OE Pin Description
OE#
Device State
Comments
Asserted (low voltage)
Differential input buffers and output buffers
enabled. Input impedance = 50Ω
Normal functioning state for IN_D to OUT_D
level shifting function.
Unasserted (high voltage)
Low-power state.
à
Differential input buffers and termination
are disabled.
à
Differential inputs are in a high
impedance state.
à
OUT_D level-shifting outputs are
disabled.
à
OUT_D level-shifting outputs are in high
impedance state.
à
Internal bias currents are turned off.
Intended for lowest power condition when:
à
No display is plugged in or
à
The level shifted data path is disabled
HPD_SINK input and HPD_SOURCE
output are not affected by OE# SCL_
SOURCE, SCL_SINK, SDA_SOURCE
and SDA_SINK signals and functions
are not affected by OE#
Test Setup Condition
VDD = 3.3V, Ambient temperature 25°C
Rise/Fall time is from 20% to 80% on Rising/Falling edge
Date rate: 620 Mbps
Input: 1V differential peak-to-peak clock pattern
Equalization : 3dB
12-0236



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com