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IO20PDB0V0 датащи(PDF) 168 Page - Microsemi Corporation |
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IO20PDB0V0 датащи(HTML) 168 Page - Microsemi Corporation |
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168 / 197 page ![]() Pin Descriptions 5- 54 R e v i sio n 1 2 AA13 NC ADC10 AA14 NC ADC9 AA15 NC GND15ADC2 AA16 MAINXIN MAINXIN AA17 MAINXOUT MAINXOUT AA18 LPXIN LPXIN AA19 LPXOUT LPXOUT AA20 NC NC AA21 NC NC AA22 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26 AB1 GND GND AB2 GPIO_13/IO36RSB4V0 GPIO_13/IO45RSB4V0 AB3 GPIO_14/IO35RSB4V0 GPIO_14/IO44RSB4V0 AB4 GND GND AB5 PCAP PCAP AB6 NCAP NCAP AB7 ABPS3 ABPS3 AB8 ADC3 ADC3 AB9 GND15ADC0 GND15ADC0 AB10 VCC33ADC1 VCC33ADC1 AB11 VAREF1 VAREF1 AB12 TM2 TM2 AB13 CM2 CM2 AB14 ABPS4 ABPS4 AB15 GNDAQ GNDAQ AB16 GNDMAINXTAL GNDMAINXTAL AB17 GNDLPXTAL GNDLPXTAL AB18 VCCLPXTAL VCCLPXTAL AB19 VDDBAT VDDBAT AB20 PTBASE PTBASE AB21 NC NC AB22 GND GND B1 EMC_DB[15]/GAA2/IO71PDB5V0 EMC_DB[15]/GAA2/IO88PDB5V0 B2 GND GND Pin Number FG484 A2F200 Function A2F500 Function Notes: 1. Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 2. *: Indicates that the signal assigned to the pins as a CLKBUF/CLKBUF_LVPECL/CLKBUF_LVDS goes through a glitchless mux. In order for the glitchless mux to operate correctly, the signal must be a free-running clock signal. Refer to the ’Glitchless MUX’ section in the SmartFusion Microcontroller Subsystem User’s Guide for more details. |
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