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IO20PDB0V0 датащи(PDF) 158 Page - Microsemi Corporation |
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IO20PDB0V0 датащи(HTML) 158 Page - Microsemi Corporation |
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158 / 197 page ![]() Pin Descriptions 5- 44 R e v i sio n 1 2 B16 GNDQ GNDQ GNDQ C1 EMC_DB[14]/IO45NDB5V0 EMC_DB[14]/GAB2/IO71NDB5V0 EMC_DB[14]/GAB2/IO88NDB5V0 C2 VCCPLL0 VCCPLL VCCPLL0 C3 EMC_BYTEN[0]/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0 C4 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 C5 EMC_CS0_N/IO01NDB0V0 EMC_CS0_N/GAB0/IO01NDB0V0 EMC_CS0_N/GAB0/IO05NDB0V0 C6 EMC_CS1_N/IO01PDB0V0 EMC_CS1_N/GAB1/IO01PDB0V0 EMC_CS1_N/GAB1/IO05PDB0V0 C7 GND GND GND C8 EMC_AB[8]/IO08NDB0V0 EMC_AB[8]/IO08NDB0V0 EMC_AB[8]/IO13NDB0V0 C9 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO11PDB0V0 C10 VCCFPGAIOB0 VCCFPGAIOB0 VCCFPGAIOB0 C11 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO17PDB0V0 C12 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO18PDB0V0 C13 GND GND GND C14 GCC0/IO18NPB0V0 GBA2/IO20PPB1V0 GBA2/IO27PPB1V0 C15 GCB0/IO19NDB0V0 GCA2/IO23PDB1V0 GCA2/IO28PDB1V0 * C16 GCB1/IO19PDB0V0 IO23NDB1V0 IO28NDB1V0 D1 VCCFPGAIOB5 VCCFPGAIOB5 VCCFPGAIOB5 D2 VCOMPLA0 VCOMPLA VCOMPLA0 D3 GND GND GND D4 GNDQ GNDQ GNDQ D5 EMC_CLK/IO00NDB0V0 EMC_CLK/GAA0/IO00NDB0V0 EMC_CLK/GAA0/IO02NDB0V0 D6 EMC_RW_N/IO00PDB0V0 EMC_RW_N/GAA1/IO00PDB0V0 EMC_RW_N/GAA1/IO02PDB0V0 D7 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO12NDB0V0 D8 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO12PDB0V0 D9 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO11NDB0V0 D10 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO19NDB0V0 D11 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO19PDB0V0 D12 GNDQ GNDQ GNDQ D13 GCC1/IO18PPB0V0 GBB2/IO20NPB1V0 GBB2/IO27NPB1V0 D14 GCA0/IO20NDB0V0 GCB2/IO24PDB1V0 GCB2/IO33PDB1V0 Pin No. FG256 A2F060 Function A2F200 Function A2F500 Function Notes: 1. Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 2. *: Indicates that the signal assigned to the pins as a CLKBUF/CLKBUF_LVPECL/CLKBUF_LVDS goes through a glitchless mux. In order for the glitchless mux to operate correctly, the signal must be a free-running clock signal. Refer to the ’Glitchless MUX’ section in the SmartFusion Microcontroller Subsystem User’s Guide for more details. |
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