ZADCS146/147

12-Bit, 200ksps, ADC Family

Data Sheet

October 12, 2011

© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

19 of 25

Figure 11: 16-Clock External Clock Mode Conversion

DOUT

SSTRB

DIN

SCLK

nCS

8

1

8

1

S

BIP

SGL/

DIF

PD1 PD0

(MSB)

B11 B10 B9 B8 B7 B6 B5

B4

B3 B2 B1 B0

Zero filled

(Start)

Idle

(LSB)

1

8

UNI/

BIP

SGL/

DIF

PD1 PD0

B11 B10

1

Acquire

A0

A1

A2

S

Acquire

Idle

Conversion

Figure 12: 15-Clock External Clock Mode Conversion

SCLK

nCS

1

8

1

S

BIP

SGL/

DIF

PD1 PD0

B11 B10 B9 B8 B7

DOUT

SSTR

DIN

(MSB)

B6 B5

B3 B2 B1 B0

Zero filled

(Start)

Acquire

Idle

Conversion

(LSB)

1

BIP

SGL/

DIF

PD1 PD0

Acquire

B11 B10

1

1

B9 B8 B7 B6 B5 B4

S

A2

Conversion

B4

S

Internal Clock Mode

In Internal Clock Mode, the conversion starts at the falling clock edge of the eighth control bit just as in

External Clock Mode. However, there are no further clock pulses required at SCLK to complete the

conversion. The conversion clock is generated by an internal oscillator that runs at approximately 3.2MHz.

While the conversion is running, the SSTRB signal is driven LOW. As soon as the conversion is complete,

SSTRB is switched to HIGH, signalling that the conversion result can be read out on the serial interface. To

shorten cycle times ZADCS146 and ZADCS147 devices allow interleaving of the read out process with the

transmission of a new control byte. Thus it is possible to read the conversion result and to start a new

conversion with just two consecutive byte transfers, instead of thee bytes that would have to be send without

the interleaving function. While the IC is performing a conversion in Internal Clock Mode, the Chip Select

signal (nCS) may be tied HIGH allowing other devices to communicate on the bus. The output driver at DOUT

specified limits depending on the actual VDD and temperature values.

16-Clocks per Conversion

Interleaving of the data read out process and transmission of a new Control Byte is also supported for

External Clock Mode operation. Figure 11 shows the transmission timing for conversion runs using 16 clock

cycles per run.

15-Clocks per Conversion

ZADCS146 and ZADCS147 do also support a 15 clock cycle conversion mode (see Figure 12). This is the

fastest conversion mode possible. In fact, the specified converter sampling rate of 200ksps will be reached in

this mode, provided the clock frequency is set to 3.2MHz. Usually micro controllers do not support this kind of

15 bit serial communication transfers. However, specifically designed digital state machines implemented in

Field Programmable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC) may use this

operation mode.