ZADCS147 datasheet(16/26 Pages) ETC2

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ZADCS146/147

12-Bit, 200ksps, ADC Family

Data Sheet

October 12, 2011

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

16 of 25

In bipolar mode, IN+ can range from (IN– - Vref/2) to

(IN–+Vref/2) keeping the converter out of code

saturation. For instance, if IN– is set to a constant DC

voltage of Vref/2, then IN+ can vary from 0V to VREF to

cover the entire code range. Lower or higher voltages of

IN+ keep the output code at the minimum or maximum

code value.

Figure 5 shows the input voltage ranges in bipolar mode

when IN– is set to a constant DC voltage.

As explained before, ZADCS146 /ZADCS147 can also

be used to convert fully differential input signals that

change around a common mode input voltage.

The bipolar mode is best used for such purposes since

it allows the input signals to be positive or negative in

relation to each other.

The common mode level of a differential input signal is

calculated VCM = (V(IN+)+ V(IN–)) / 2. To avoid code

clipping or over steering of the converter, the common

mode level can change from ¼ VREF … ¾ VREF. Within

this range the peak to peak amplitude of the differential

input signal can be ± VREF/2.

The average input current on the analog inputs depends

on the conversion rate. The signal source must be

capable of charging the internal sampling capacitors

(typically 16pF on each input of the converter: IN+ and

IN–) within the acquisition time tACQ to the required

accuracy. The equivalent input circuit in sampling mode

is shown in Figure 7.

The following equation provides a rough hand calculation for a source impedance RS that is required to settle

out a DC input signal referenced to AGND with 8 bit accuracy in a given acquisition time

ACQ







For example, if fSCLK = 3.2MHz, the acquisition

time

tACQ = 781.25ns. Thus the output

impedance of the signal source RS must be less

than

1.34kΩ

kΩ

20pF

781.25ns









If the output impedance of the source is higher

than the calculated maximum RS the acquisition

time must be extended by reducing fSCLK to

ensure 8 bit accuracy. Another option is to add a

capacitor of > 20nF to the individual input.

Although this limits the bandwidth of the input

signal because an RC low pass filter is build

together with the source impedance, it may be useful for certain applications.

Figure 6: Block diagram of input multiplexer

Shown configuration

Figure 7: Equivalent input circuit during sampling

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

A2 … A0 = 0x000

IN+

Converter

IN-

COM

SGL/DIF = HIGH

See Table 3 & Table 4

for Coding Schemes

RSW

CHOLD+

16pF

CIN

4pF

RSW

CH0

AGND

CHOLD-

16pF

CIN

4pF

AGND

IN+

IN-

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

Channel

Multiplexer

3kΩ

VDC

3kΩ

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