ZADCS146/147

12-Bit, 200ksps, ADC Family

Data Sheet

October 12, 2011

© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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2.2.

Analog Input

Block diagram at front page) get sampled during the acquisition period enabling the converter to be used in

fully differential applications where both signals can vary over time.

The ZADCS146 /ZADCS147 converters do not require that the negative input signal be kept constant within

± 0.5LSB during the entire conversion as is commonly required by converters featuring pseudo differential

operation only.

The input signals can be applied single ended, referenced to the COM pin, or differential, using pairs of the

input channels. The desired configuration is selectable for every conversion via the Control-Byte received on

DIN pin of the digital interface (see further description below)

A block diagram of the input multiplexer is shown in Figure 6. Table 3 and Table 4 show the relationship of the

Control-Byte bits A2, A1, A0 and SGL/DIF to the configuration of the analog multiplexer.

depending on the selected conversion mode – uniploar or bipolar – certain input voltage relations can limit the

output code range of the converter.

voltage is clamped at VDD + 0.2V by ESD protection devices.

Figure 4: Input voltage range in unipolar mode

Figure 5: Input voltage range for bipolar mode

V

V

IN+

CM

mentioned VDD condition is true. See also Figure 4 for input voltage ranges in unipolar conversion mode.

0V

Code Range

0xFF

0x00

0V

¾

V

Range

-V

/2

0V

+V

/2

V

REF

REF

DIFF