ZADCS146/147

12-Bit, 200ksps, ADC Family

Data Sheet

October 12, 2011

© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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2

Detailed Description

2.1.

General Operation

The ZADCS14x are classic successive approximation register (SAR) type converters. The architecture is

based on a capacitive charge redistribution DAC merged with a resistor string DAC building a hybrid converter

with excellent monotonicity and DNL properties. The Sample & Hold function is inherent to the capacitive

DAC. This avoids additional active components in the signal path that could distort the input signal or

introduce errors.

Both devices ZADCS146 / ZADCS147 build on the same converter core and differ only in the availability of an

internal reference voltage generator. ZADCS146 is equipped with a highly accurate internal 1.25V bandgap

reference which is available at the VREFADJ pin. The bandgap voltage is further amplified by an internal

buffer amplifier to 2.50V that is available at pin VREF. ZADCS147 comes without the internal reference and

the internal buffer amplifier. It requires an external reference supplied at VREF, with the benefit of

considerably lower power consumption.

A basic application schematic for ZADCS146 is shown in Figure 2, for ZADCS147 in Figure 3. ZADCS146 can

also be operated with an external reference, if VREFADJ is tied to VDD.

Figure 2: Basic application schematic for ZADCS146

Figure 3: Basic application schematic for ZADCS147

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

0

0

0

IN+

IN-

1

0

0

IN+

IN-

0

0

1

IN+

IN-

1

0

1

IN+

IN-

0

1

0

IN+

IN-

1

1

0

IN+

IN-

0

1

1

IN+

IN-

1

1

1

IN+

IN-

Table 3: Channel selection in Single Ended Mode

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

0

0

0

IN+

IN-

0

0

1

IN+

IN-

0

1

0

IN+

IN-

0

1

1

IN+

IN-

1

0

0

IN-

IN+

1

0

1

IN-

IN+

1

1

0

IN-

IN+

1

1

1

IN-

IN+

Table 4: Channel selection in Differential Mode

Single-ended or differential

analog inputs, 0V … +2.5V

nCS

1

DIN

2

DGND

3

AGND

4

5

COM

6

CH0

7

CH1

8

CH4

9

CH5

10

SCLK 20

SSTRB 19

DOUT 18

nSHDN 17

VDD 16

CH2 14

CH3 13

CH6 12

CH7 11

ZADCS146

47nF

≥ 4.7µF

0.1µF

10µF

µC

+2.7V to 5.25V

Single-ended or differential

nCS

1

DIN

2

DGND

3

AGND

4

5

COM

6

CH0

7

CH1

8

CH4

9

CH5

10

SCLK 20

SSTRB 19

DOUT 18

nSHDN 17

VDD 16

n.c. 15

CH2 14

CH3 13

CH6 12

CH7 11

ZADCS147

≥ 4.7µF

0.1µF

µC

+2.7V to 5.25V

10µF