CS43L42 datasheet(27/40 Pages) CIRRUS

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CS43L42

DS481PP2

DEM0 and DEM1

(Stand-Alone Mode)

4 and 5

De-emphasis Control (Input) - Selects the appropriate digital filter to maintain the standard

µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Fig-

ure 30) When using Internal Serial Clock Mode, Pin 5 is available for de-emphasis control,

DEM1, and all de-emphasis filters are available. When using External Serial Clock Mode,

Pin 5 is not available for de-emphasis use and only the 44.1 kHz de-emphasis filter is avail-

able. (see Table 9)

Note:

De-emphasis is not available in High-Rate Mode.

Interface Power (Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC.

MCLK

Master Clock (Input) - Frequency must be either 256x, 384x, 512x, 768x or 1024x the input

sample rate in Base Rate Mode (BRM) and 128x, 192x, 256x or 384x the input sample rate

in High Rate Mode (HRM). Note that some multiplication factors require setting the

MCLKDIV bit (see Master Clock DIVIDE ENABLE (mclkdiv)). Tables 10 and 11 illustrate

several standard audio sample rates and the required master clock frequencies.

SCL/CCLK

(Control Port Mode)

Serial Control Interface Clock (Input) - Clocks the serial control data into or out of

SDA/CDIN.

SDA/CDIN

(Control Port Mode)

Serial Control Data I/O (Input/Output) - In Two-Wire mode, SDA is a data I/O line. CDIN is

the input data line for the control port interface in SPI mode.

Internal SCLK

External SCLK

DEM1

DEMO

DESCRIPTION

DEMO

DESCRIPTION

Disabled

44.1kHz

44.1 kHz

48kHz

32kHz

Table 9. Stand Alone De-Emphasis Control

Sample Rate

(kHz)

MCLK (MHz)

HRM

128x

192x

256x*

384x*

4.0960

6.1440

8.1920

12.2880

44.1

5.6448

8.4672

11.2896

16.9344

6.1440

9.2160

12.2880

18.4320

8.1920

12.2880

16.3840

24.5760

88.2

11.2896

16.9344

22.5792

33.8688

12.2880

18.4320

24.5760

36.8640

* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).

Table 10. HRM Common Clock Frequencies

Sample Rate

(kHz)

MCLK (MHz)

BRM

256x

384x

512x

768x*

1024x*

8.1920

12.2880

16.3840

24.5760

32.7680

44.1

11.2896

16.9344

22.5792

32.7680

45.1584

12.2880

18.4320

24.5760

36.8640

49.1520

* Requires MCLKDIV bit = 1 in Mode Control 2 register (address 0Bh).

Table 11. BRM Common Clock Frequencies

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