CS43L42

24

DS481PP2

4.11 Mode Control 2 (address 0Bh)

4.11.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0

0 - Disabled

1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other

internal circuitry.

Note:

Internal SCLK is not available when this function is enabled.

4.11.2 LINE AMPLIFIER GAIN COMPENSATION (LINE)

Default = 00

00 - 0.785 x VA

01 - 0.943 x VA

10 - 1.571 x VA

11 - Line Mute

Function:

The Line Amplifier Gain Compensation bits allow the user to scale the full-scale line output level according

to the power supply voltage used. The full-scale line output level will be equal to {gain factor}xVA, where

{gain factor} is selected from options above. For example, if the user wants the full-scale line output volt-

1.571.

Note:

It is possible to exceed the maximum output level, limited by VA_LINE, by incorrectly setting the

gain compensation factor.

The Line Mute option is available to allow muting of the line output when the headphone output is still in

use and the line amp is still powered up. To use this feature, first mute the outputs via the ATAPI bits.

Next, set the LINE GAIN to Line Mute. Finally, un-mute the outputs with the ATAPI bits. Following these

steps will ensure a click free mute.

4.11.3 DIGITAL INTERFACE FORMAT (DIF)

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital

Interface Format and the options are detailed in Figures 19-25.

Note:

Internal SCLK is not available when MCLKDIV is enabled.

7

654

32

10

MCLKDIV

LINE1

LINE0

RESERVED

RESERVED

DIF2

DIF1

DIF0

0

000

00

00