CS43L41 datasheet(26/36 Pages) CIRRUS

26 / 36 page

CS43L41

DS473PP1

Control function can enable the system designer to

achieve idle channel noise/signal-to-noise ratios

which are only limited by the external mute circuit.

7. CONTROL PORT INTERFACE

The control port is used to load all the internal set-

tings of the CS43L41. The operation of the control

port may be completely asynchronous to the audio

sample rate. However, to avoid potential interfer-

ence problems, the control port pins should remain

static if no operation is required. *

The control port has 2 modes: SPI and I2C compat-

ible, with the CS43L41 operating as a slave device

in both modes. If I2C operation is desired, AD0/CS

should be tied to VA or AGND. If the CS43L41

ever detects a high to low transition on AD0/CS af-

ter power-up, SPI mode will be selected. The con-

trol port registers are write-only in SPI mode.

7.1

SPI Mode

In SPI mode, CS is the CS43L41 chip select signal,

CCLK is the control port bit clock, CDIN is the in-

put data line from the microcontroller and the chip

address is 0010000. All signals are inputs and data

is clocked in on the rising edge of CCLK.

Figure 7 shows the operation of the control port in

SPI mode. To write to a register, bring CS low. The

first 7 bits on CDIN form the chip address, and

must be 0010000. The eighth bit is a read/write in-

dicator (R/W), which must be low to write. The

next 8 bits form the Memory Address Pointer

(MAP), which is set to the address of the register

that is to be updated. The next 8 bits are the data

which will be placed into the register designated by

the MAP.

The CS43L41 has MAP auto increment capability,

enabled by the INCR bit in the MAP register. If

INCR is 0, then the MAP will stay constant for suc-

cessive writes. If INCR is set to 1, then MAP will

auto increment after each byte is written, allowing

block reads or writes of successive registers.

7.2

I2C Compatible Mode

In I2C compatible mode, SDA is a bi-directional

data line. Data is clocked into and out of the part by

the clock, SCL, with the clock to data relationship

as shown in Figure 8. There is no CS pin. Pin AD0

forms the partial chip address and should be tied to

VA or AGND as required. The upper 6 bits of the

7-bit address field must be 001000. To communi-

cate with the CS43L41 the LSB of the chip address

field, which is the first byte sent to the CS43L41,

should match the setting of the AD0 pin. The eighth

bit of the address byte is the R/W bit (high for a

read, low for a write). If the operation is a write, the

next byte is the Memory Address Pointer, MAP,

which selects the register to be read or written. The

MAP is then followed by the data to be written. If

the operation is a read, then the contents of the reg-

ister pointed to by the MAP will be output after the

chip address.

The CS43L41 has MAP auto increment capability,

enabled by the INCR bit in the MAP register. If

INCR is 0, then the MAP will stay constant for suc-

cessive writes. If INCR is set to 1, then MAP will

auto increment after each byte is written, allowing

block reads or writes of successive registers.

For more information on I2C, please see “The I2C-

Bus Specification: Version 2.0”, listed in the Ref-

erences section.

* The MCLK is required for both control port inter-

faces.

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