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CS43L41 датащи(PDF) 23 Page - Cirrus Logic

номер детали CS43L41
подробное описание детали  Low Power 24-Bit, 96 kHz DAC with Volume Control?
PDF  36 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L41 датащи(HTML) 23 Page - Cirrus Logic

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CS43L41
DS473PP1
23
Master Clock - MCLK
Pin 5, Input
Function:
The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Base
Rate Mode (BRM) and 128x, 192x, 256x or 384x the input sample rate in High Rate Mode (HRM). Note
that some multiplication factors require setting the MCLKDIV bit in the MCLK Control Register. Table 12
illustrates several standard audio sample rates and the required master clock frequencies.
Left/Right Clock - LRCK
Pin 4, Input
Function:
The Left/Right clock determines which channel is currently being input on the serial audio data input, SDA-
TA. The frequency of the Left/Right clock must be at the input sample rate. Audio samples in Left/Right
sample pairs will be simultaneously output from the digital-to-analog converter whereas Right/Left pairs
will exhibit a one sample period difference. The required relationship between the Left/Right clock, serial
clock and serial data is defined by the Mode Control Byte and the options are detailed in Figures 20-26.
Serial Audio Data - SDATA
Pin 2, Input
Function:
Two’s complement MSB-first serial data is input on this pin. The data is clocked into SDATA via the serial
clock and the channel is determined by the Left/Right clock. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-
tailed in Figures 20-26.
Sample Rate
(kHz)
MCLK (MHz)
HRM
BRM
128x
192x
256x*
384x*
256x
384x
512x
768x*
1024x*
32
4.0960
6.1440
8.1920
12.2880
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
5.6448
8.4672
11.2896
16.9344
11.2896
16.9344
22.5792
32.7680
45.1584
48
6.1440
9.2160
12.2880
18.4320
12.2880
18.4320
24.5760
36.8640
49.1520
64
8.1920
12.2880
16.3840
24.5760
-
-
-
-
-
88.2
11.2896
16.9344
22.5792
33.8688
-
-
-
-
-
96
12.2880
18.4320
24.5760
36.8640
-
-
-
-
-
* Requires MCLKDIV bit = 1 in MCLK Control Register (address 00h)
Table 12. Common Clock Frequencies



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