CS43L41

24

DS473PP1

Serial Clock - SCLK

Pin 3, Input

Function:

Clocks the individual bits of the serial data into the SDATA pin. The required relationship between the

Left/Right clock, serial clock and serial data is defined by the Mode Control Byte and the options are de-

tailed in Figures 20-26.

The CS43L41 supports both internal and external serial clock generation modes. The Internal Serial Clock

Mode eliminates possible clock interference from an external SCLK. Use of the Internal Serial Clock Mode

is always preferred.

Internal Serial Clock Mode

In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with the master

clock and left/right clock. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data

format, as shown in Figures 20-26. Operation in this mode is identical to operation with an external serial

clock synchronized with LRCK.

External Serial Clock Mode

The CS43L41 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected

on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode

if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.

Reset - RST

Pin 1, Input

Function:

The device enters a low power mode and all internal registers are reset to the default settings, including

the control port, when low. When high, the control port becomes operational and the PDN bit must be

cleared before normal operation will occur. The control port can not be accessed when reset is low.

Serial Control Interface Clock - SCL/CCLK

Pin 6, Input

Function:

Clocks the serial control data into or from SDA/CDIN.

Serial Control Data I/O - SDA/CDIN

Pin 7, Input/Output

Function:

Address Bit / Chip Select - AD0/CS

Pin 8, Input

Function:

device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device

has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.

Mute Control - MUTEC

Pin 16, Output

Function:

The Mute Control pin goes high during power-up initialization, reset, muting, master clock to left/right clock

frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute

circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not

mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops.