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CS43L41 датащи(PDF) 11 Page - Cirrus Logic

номер детали CS43L41
подробное описание детали  Low Power 24-Bit, 96 kHz DAC with Volume Control?
PDF  36 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L41 датащи(HTML) 11 Page - Cirrus Logic

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CS43L41
DS473PP1
11
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, CL = 30 pF)
Notes: 12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For FSCK < 1 MHz
Parameter
Symbol
Min
Max
Unit
SPI® Mode
CCLK Clock Frequency
fsclk
-6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling
(Note 12)
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 13)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 14)
tr2
-100
ns
Fall Time of CCLK and CDIN
(Note 14)
tf2
-100
ns
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCLK
CDIN
t css
t csh
t spi
t srs
RST
Figure 5. SPI Control Port Timing



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