CS43L41

DS473PP1

15

4.

REGISTER BIT DESCRIPTION

4.1

MASTER CLOCK DIVIDE ENABLE

MCLK Control Register (address 00h)

Access:

Default:

0 - Disabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.

Note: This feature is present on revision C and newer devices. For backward compatibility with pre-

vious revision devices, this bit defaults to zero.

4.2

AUTO-MUTE

Mode Control Register (address 01h)

Access:

Default:

1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio

samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and mut-

ing is done independently for each channel. The quiescent voltage on the output will be retained and

the Mute Control pin will go active during the mute period. The muting function is effected, similar to

volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.

765

4321

0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

MCLKDIV

Reserved

MCLKDIV

MODE

0

Disabled

1

Enabled

Table 1. Master Clock Divide Enable

765

4321

0

AMUTE

DIF2

DIF1

DIF0

DEM1

DEM0

POR

PDN

AMUTE

MODE

0

Disabled

1

Enabled

Table 2. Auto-Mute Enable