CS4218 datasheet(42/44 Pages) CIRRUS

42 / 44 page

To load control data into the codec, three HC597’s are utilized. These are the latches that store the

DSP-sent control data, and shift registers that shift the data into the codec. The codec uses an inverted

SSYNC signal to copy the latches to the shift registers every frame. In this diagram the DSP is as-

sumed to have a data bus bandwidth of at least 24 bits. If the DSP has less than 24-bits, the three

HC597s must be split into two addresses. Since the HC597 internal latches are copied to the shift

registers, the latches continually hold the DSP-sent data; therefore, the DSP only needs to write data to

the latches when a change is desired.

The second section is comprised of an HC595 shift register and latch that is clocked by an inverted

SCLK. The data shifted into the HC595 is transferred to the HC595’s latch by the SSYNC signal. This

HC595 captures the 8 bits prior to the SSYNC signal (which is also MF4:CCS) going high. As shown

in Figure 12, and assuming the MF4:CCS (SSYNC) signal rises at bit 32, the 8-bits prior to MF4:CCS

rising are a copy of all the important status bits. This allows one shift register to capture all the

important information. The interrupt pin cannot reliably be used in this configuration since the interrupt

pin is cleared by reading the control port which occurs asynchronously (every audio frame) with re-

spect to the interrupt occurrence.

The third section is only needed if sample frequencies need to be changed. This section is comprised of

an HC574 octal latch that can be replaced by general purpose port pins if available. This section

controls the sample frequency selection bits: MF6:F1, MF7:F2, MF8:F3 and the RESET pin. A change

in sample rate automatically initiates a calibration cycle.

CS4218

DS135F1

CS4218 датащи(PDF) 42 Page - Cirrus Logic