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CS4218 датащи(PDF) 25 Page - Cirrus Logic |
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CS4218 датащи(HTML) 25 Page - Cirrus Logic |
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25 / 44 page ![]() SERIAL MODE 5 (SM5) The Serial Mode 5 is compatible with the Phil- lips I 2S serial protocol. SM5 is enabled by setting SMODE3 = 0, SMODE2 = 0, and SMODE1 = 1. This is a master mode fixed at 64 BPF. Figure 21 shows the frame format of the SM5. Figure 22 shows the detailed frame format. The multi-function pins MF4, MF7, and MF8 are not used in this mode. MF4 should be tied to VD, and MF7 and MF8 should be tied to ground. Figures 11 & 12 illustrate the serial data in, SDIN, and serial data out, SDOUT, sub-frames for SM5. Sample Frequency Selection The multifunction pins MF1:F1, MF2:F2, and MF3:F3 are used to select the sample frequency divider. Table 3 lists the decoding for the sample frequency select pins where the sample fre- quency selected is CLKIN/N. Also shown are the sample frequencies obtained by using one of two example master clocks. A change in sample rate will automatically initiate a calibration cycle. Word A Word B FRAME n 64 SCLK Periods Word A Word B FRAME (n+1) Word A Word B FRAME (n+2) Word A Word B FRAME (n+3) Word A Word B FRAME (n+4) SSYNC DATA 1 SCLK Figure 21. Serial Mode 5 MSB SCLK SSYNC MSB 32 CLOCKS 32 CLOCKS LSB Word A Word B LSB SDIN SDOUT LSB FRAME Figure 22. Detailed Serial Mode 5. CS4218 DS135F1 25 |
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