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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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S29GL01GS датащи(PDF) 86 Page - SPANSION |
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S29GL01GS датащи(HTML) 86 Page - SPANSION |
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86 / 106 page  86 GL-S MirrorBit® Family S29GL_128S_01GS_00_08 October 9, 2013 Da ta Sh e e t Figure 10.13 Read to Write (CE# Toggle) Operation Timing Diagram Notes: 1. Not 100% tested. 2. Upon the rising edge of WE#, must wait tSR/W before switching to another address. 3. See Table 5.4 on page 46 and Table 5.5 on page 47 for specific values. Table 10.8 Erase/Program Operations Parameter Description VIO = 2.7V to VCC VIO = 1.65V to VCC Unit JEDEC Std tWHWH1 tWHWH1 Write Buffer Program Operation Typ (Note 3) µs Effective Write Buffer Program Operation per Word Typ (Note 3) µs Program Operation per Word or Page Typ (Note 3) µs tWHWH2 tWHWH2 Sector Erase Operation (Note 1) Typ (Note 3) ms tBUSY Erase/Program Valid to RY/BY# Delay Max 80 ns tSR/W Latency between Read and Write operations (Note 2) Min 10 ns tESL Erase Suspend Latency Max (Note 3) µs tPSL Program Suspend Latency Max (Note 3) µs tRB RY/BY# Recovery Time Min 0 µs Amax-A0 CE# OE# WE# DQ15-DQ0 tACC tOE tCE tAS tCS tDS tAH tDH tWP tCH tOH tOH tOH tDF tDF tGHWL |
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