COM20020ILJP datasheet(69/72 Pages) MICROCHIP

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5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

SMSC COM20020I Rev D

Page 69

Revision 12-05-06

DATASHEET

synchronized between the CPU and COM20020ID. Thus, changing the CKP3-1 timing does not

synchronize with the internal clocks of Pre-Scalar, and changing CKP3-1 may cause spike noise to appear

on the output clock line.

Setting the EF bit will include flip-flops inserted between the Configuration register and Pre-Scalar for

synchronizing the CKP3-1 with Pre-Scalar’s internal clocks.

Never change the CKP3-1 when the data rate is over 5 Mbps. They must all be zero.

Shorten The Write Interval Time To The Command Register

The COM20020ID limits the write interval time for continuous writing to the Command register. The

minimum interval time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6

μS at the 156.25

Kbps. This 1.6

μS is very long for CPU.

Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to XTAL

clock which is not changed by the data rate, such that the minimum interval time becomes 100 nS.

Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands

The COM20020ID has a write prohibition period for writing the Enable Transmit/Receive Commands. This

period is started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by

setting the TA/RI bit with a pulse signal. It is 3.2

μS at 156.25 Kbps. This period may be a problem when

using interrupt processing. The interrupt occurrs when the RI bit returns to High. The CPU writes the next

Enable Receive Command to the other page immediately. In this case, the interval time between the

interrupt and writing Command is shorter than 3.2

μS.

Setting the EF bit will cause the TA/RI bit to return to High upon release of the pulse signal for setting the

TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 0.1 on the following page.

The EF bit also controls the resolution of the following issues from the COM20020 Rev. B:

Network MAP Generation

Tentative ID is used for generating the Network MAP, but it sometimes detects a non-existent node. Every

time the Tentative-ID register is written, the effect of the old Tentative-ID remains active for a while, which

results in an incorrect network map. It can be avoided by a carefully coded software routine, but this

requires the programmer to have deep knowledge of how the COM20020ID works. Duplicate-ID is mainly

used for generating the Network MAP. This has the same issue as Tentative-ID.

A minor logic change clears all the remaining effects of the old Tentative-ID and the old Duplicate-ID, when

the COM20020ID detects a write operation to Tentative-ID or Node-ID register. With this change,

programmers can use the Tentative-ID or Duplicate-ID for generating the network MAP without any issues.

This change is Enabled/Disabled by the EF bit.

Mask Register Reset

The Mask register is reset by a soft reset in the COM20020 Rev. A, but is not reset in Rev. B. The Mask

every time the soft reset happens, the COM20020 Rev. B generates an unnecessary interrupt since the

status bits RI and TA are back to one by the soft reset.

This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft

reset. The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in

the Configuration register. This solution is Enabled/Disabled by the EF bit.

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