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COM20020ILJP датащи(PDF) 59 Page - Microchip Technology

номер детали COM20020ILJP
подробное описание детали  5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
PDF  72 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

COM20020ILJP датащи(HTML) 59 Page - Microchip Technology

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5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D
Page 59
Revision 12-05-06
DATASHEET
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t6
t4
t2
nDS
DIR
t5
t7
t10
t11
Note 2
Parameter
min
max
units
t1
t2
t3
t4
t5
t6
t7
15
10
5**
0
nS
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Low)
DIR Hold from nDS Inactive
4TARB
*
nS
nS
nS
nS
nS
nS
t8
nS
nDS Low to Valid Data
40**
t9
t10
t11
nS
nS
nS
nDS High to Data High Impedence
nDS Low Width
nDS High Width
20
10
10
0
60
20
CASE 1: RBUSTMG bit = 0
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
nCS may become active after control becomes active, but the access time (t8) will
now be 45nS measured from the leading edge of nCS.
**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.



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