COM20020ILJP datasheet(3/72 Pages) MICROCHIP

3 / 72 page

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

SMSC COM20020I Rev D

Page 3

Revision 12-05-06

DATASHEET

Table of Contents

Chapter 1

General Description................................................................................................................ 6

Chapter 2

Pin Configurations .................................................................................................................. 7

Chapter 3

Description of Pin Functions .................................................................................................. 9

Chapter 4

Protocol Description ............................................................................................................. 12

4.1

Network Protocol ........................................................................................................................................12

4.2

Data Rates .................................................................................................................................................12

4.2.1

Selecting Clock Frequencies Above 2.5 Mbps ....................................................................................12

4.3

Network Reconfiguration ............................................................................................................................13

4.4

Broadcast Messages..................................................................................................................................14

4.5

Extended Timeout Function .......................................................................................................................14

4.5.1

Response Time ...................................................................................................................................14

4.5.2

Idle Time .............................................................................................................................................14

4.5.3

Reconfiguration Time ..........................................................................................................................14

4.6

Line Protocol ..............................................................................................................................................14

4.6.1

Invitations To Transmit........................................................................................................................15

4.6.2

Free Buffer Enquiries ..........................................................................................................................15

4.6.3

Data Packets.......................................................................................................................................15

4.6.4

Acknowledgements .............................................................................................................................16

4.6.5

Negative Acknowledgements ..............................................................................................................16

Chapter 5

System Description ..............................................................................................................17

5.1

Microcontroller Interface.............................................................................................................................17

5.1.1

High Speed CPU Bus Timing Support ................................................................................................20

5.2

Transmission Media Interface ....................................................................................................................21

5.2.1

Traditional Hybrid Interface .................................................................................................................21

5.2.2

Backplane Configuration .....................................................................................................................21

5.2.3

Differential Driver Configuration ..........................................................................................................23

5.2.4

Programmable TXEN Polarity .............................................................................................................23

Chapter 6

Functional Description..........................................................................................................26

6.1

Microsequencer..........................................................................................................................................26

6.2

Internal Registers .......................................................................................................................................27

6.2.1

Interrupt Mask Register (IMR) .............................................................................................................27

6.2.2

Data Register ......................................................................................................................................28

6.2.3

Tentative ID Register ..........................................................................................................................28

6.2.4

Node ID Register.................................................................................................................................28

6.2.5

Next ID Register..................................................................................................................................28

6.2.6

Status Register....................................................................................................................................29

6.2.7

Diagnostic Status Register ..................................................................................................................29

6.2.8

Command Register .............................................................................................................................29

6.2.9

Address Pointer Registers ..................................................................................................................29

6.2.10

Configuration Register .....................................................................................................................29

6.2.11

Sub-Address Register .....................................................................................................................29

6.2.12

Setup 1 Register..............................................................................................................................30

6.2.13

Setup 2 Register..............................................................................................................................30

6.3

Internal RAM ..............................................................................................................................................40

6.3.1

Sequential Access Memory.................................................................................................................40

6.3.2

Access Speed .....................................................................................................................................40

6.4

Software Interface ......................................................................................................................................40

6.4.1

Selecting RAM Page Size ...................................................................................................................41

6.4.2

Transmit Sequence .............................................................................................................................42

6.4.3

Receive Sequence ..............................................................................................................................44

6.5

Command Chaining....................................................................................................................................45

6.5.1

Transmit Command Chaining .............................................................................................................45

6.5.2

Receive Command Chaining ..............................................................................................................46

6.6

Reset Details ..............................................................................................................................................47

6.6.1

Internal Reset Logic ............................................................................................................................47

6.7

Initialization Sequence ...............................................................................................................................47

6.7.1

Bus Determination...............................................................................................................................47

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