COM20020ILJP datasheet(35/72 Pages) MICROCHIP

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5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Datasheet

SMSC COM20020I Rev D

Page 35

Revision 12-05-06

DATASHEET

Table 6.9 - Configuration Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

Reset

RESET

A software reset of the COM20020ID is executed by writing a logic

"1" to this bit. A software reset does not reset the microcontroller

interface mode, nor does it affect the Configuration Register. The

only registers that the software reset affect are the Status Register,

the Next ID Register, and the Diagnostic Status Register. This bit

must be brought back to logic "0" to release the reset.

Command

Chaining Enable

CCHEN

This bit, if high, enables the Command Chaining operation of the

device. Please refer to the Command Chaining section for further

details. A low level on this bit ensures software compatibility with

previous SMSC ARCNET devices.

Transmit Enable

TXEN

When low, this bit disables transmissions by keeping nPULSE1,

nPULSE2 if in non-Backplane Mode, and nTXEN pin inactive.

When high, it enables the above signals to be activated during

transmissions. This bit defaults low upon reset. This bit is typically

enabled once the Node ID is determined, and never disabled during

normal operation. Please refer to the Improved Diagnostics section

for details on evaluating network activity.

4,3

Extended

Timeout 1,2

ET1, ET2

These bits allow the network to operate over longer distances than

the default maximum 2 miles by controlling the Response, Idle, and

Reconfiguration Times. All nodes should be configured with the

same timeout values for proper network operation. For the

COM20020ID with a 20 MHz crystal oscillator, the bit combinations

follow:

ET2

ET1

Response

Time (

μS)

596.6

298.4

149.2

37.4

Idle Time

(

μS)

656

328

164

Reconfig

Time (mS)

840

420

Note: These

values

are

for

5Mbps

and

RCNTMR[1,0]=00.

Reconfiguration time is changed by the RCNTMR1 and

RCNTMR0 bits.

Backplane

BACK-

PLANE

A logic "1" on this bit puts the device into Backplane Mode signaling

which is used for Open Drain and Differential Driver interfaces.

1,0

Sub Address 1,0

SUBAD 1,0

These bits determine which register at address 07 may be

accessed. The combinations are as follows:

SUBAD1

SUBAD0

Tentative ID

Node ID

Setup 1

Next ID

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