TMS320VC5470ZHKA datasheet(17/94 Pages) TI

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Introduction

December 2001 − Revised December 2002

SPRS017B

Table 2−2. Terminal Functions (Continued)

TERMINAL NAME

DESCRIPTION

I/O/Z†

MCUEN0

SPI enable trigger (edge/level, positive/negative)

EMU0−EMU1

I/O

Test emulation pins 0 and 1, active-low

TRST

Test reset input, active-low. A pulldown resistor is suggested to allow both normal device

operation and emulation.

TCK

Test Clock

TDI

Test Data Input

TDO

Test Data Output

TMS

Test Mode Select

REFCLK

Reference input clock

RESET

Chip power-on reset, active-low§¶

RESET_OUT

Reset to external peripherals, active-low

ADD00/ SDRAM_A00 −

ADD12/SDRAM_A12

MCU address bus bits 0 through 12 for Flash, SRAM, and SDRAM

ADD13−ADD17

MCU address bus bits 13 through 17 for Flash and SRAM

ADD18/ SDRAM_BA0

MCU address bus bit 18 for Flash and SRAM or SDRAM BA0 signal

ADD19/ SDRAM_BA1

MCU address bus bit 19 for Flash and SRAM or SDRAM BA1 signal

ADD20/ SDRAM_WE

MCU address bus bit 20 for Flash and SRAM or active-low SDRAM WE signal

ADD21/ SDRAM_CAS

MCU address bus bit 21 for Flash and SRAM or active-low SDRAM CAS signal

ADD22/ SDRAM_RAS

MCU address bus bit 22 for Flash and SRAM or active-low SDRAM RAS signal

CS4/ BIGEND

I/O

MCU Chip Select 4 (active-high).§ This pin is sampled at the RESET rising edge to determine

the endian mode as defined below:

0 = Little Endian

1 = Big Endian

For best results, an external pullup or pulldown should be installed to ensure proper sampling.

DATA00−DATA31

I/O

MCU data bus bits 0 through 31 for Flash, SRAM, and SDRAM

BE0/ SDRAM_DQM0

MCU byte-enable for non-SDRAM cycles, or SDRAM byte-enable (for read) and mask

(for write), active-low

BE1/ SDRAM_DQM1

MCU byte-enable for non-SDRAM cycles, or SDRAM byte-enable (for read) and mask

(for write), active-low

BE2/ SDRAM_DQM2

MCU byte-enable for non-SDRAM cycles, or SDRAM byte-enable (for read) and mask

(for write), active-low

BE3/ SDRAM_DQM3

MCU byte-enable for non-SDRAM cycles, or SDRAM byte-enable (for read) and mask

(for write), active-low

CS0

MCU chip select 0, active-low

CS1

MCU chip select 1, active-low

CS2

MCU chip select 2, active-low

CS3/ ROMSIZE16

I/O

MCU chip select 3, active-low.¶ Input sampled at RESET rising edge to determine the width of

the ARM processor during initialization as defined below:

0 = 16 bits

1 = 32 bits

For best results, an external pullup or pulldown should be installed to ensure proper sampling.

† I = input, O = output, Z = high-impedance

‡ The KBGPIO[15:8] pins include integrated pullup resistors.

§ The ARM7TDMI core can operate in either little- or big-endian mode. The 5470 configures the ARM7TDMI core’s endianness by sampling this

pin at the RESET rising edge.

¶ 5470 only supports MCU boot from a 16-bit or a 32-bit-wide memory implementation on CS0. The 5470 configures the ARM7TDMI starting

instruction size, and width of memory connected to CS0, by sampling this pin at the RESET rising edge.

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