TMS320VC5470ZHKA datasheet(39/94 Pages) TI

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MCU Subsystem Functional Overview

December 2001 − Revised December 2002

SPRS017B

4.2

MCU Memory Interface

The MCU memory interface connects the MCU to the internal and external memories and peripherals via a

32-bit-wide data bus. This bus supports MCU access sizes of 8 bits, 16 bits, and 32 bits. All peripheral control

registers are implemented as 32-bit devices and should only be accessed using 32-bit operations.

The MCU memory interface allows endian configuration. Generally, a system should be configured so that

all peripherals operate in the same endian mode. In cases where mixed endianness is used, the software

engineer must carefully control accesses to resources which are configured for the endianness that is

opposite to that of the MCU.

The MCU memory interface also provides management of external accesses. External devices supported

include ROM (Flash), SRAM, and SDRAM. The external data bus is a 32-bit bidirectional bus. The following

access management features for MCU accesses to external memory and peripherals are provided:

•

Five external chip-select signals, each with a dedicated 8M-byte range of the MCU memory map.

•

MCU access duration management (wait-state insertion) to enable the connection of slow memory

devices, and support for intercycle delays to prevent external data bus contention.

•

MCU read and write access size adaptation for MCU accesses to external non-SDRAM memory or

peripherals with 32-bit, 16-bit, and 8-bit data bus width.

•

MCU read and write access size adaptation for MCU accesses to external SDRAM memory with 32-bit

or 16-bit data bus width.

The MCU memory ranges associated with each external memory chip-select (CS0−CS3, CS4) may be

configured in little-endian or big-endian mode. The MCU processor is also configured to operate in big/little

endian mode based on the state of “BIGEND” during power-up/reset time. MCU code that accesses a

resource that is configured with a different endianness than the MCU must perform the appropriate address

calculations (depending on the data size used to write the data, and the data size being used to read the data).

4.2.1 MCU Memory Interface Wait-States

MCU accesses to internal peripherals and internal memories are generally performed at 0 wait state. SDRAM

refresh cycles delay any MCU access. MCU accesses to the API RAM require multiple clocks as determined

by the programming of the API_REG register.

Timing for MCU accesses to external SDRAM memory is controlled by SDRAM interface registers which

control CAS latency, RAS latency, back-to-back timing, refresh rate, etc. External memories or peripherals

controlled by CS0−CS3 and CS4 may be programmed to provide various cycle timings. Additionally, the WAIT

input pin may be used to insert wait-states under external hardware control.

4.2.2 MCU API Interface

The API interface, which provides MCU access to a small portion of DSP memory, provides a 16-bit data path

to the API RAM in the DSP subsystem. All 32-bit transactions are divided into two 16-bit API transactions.

The API interface supports back-to-back access with programmable insertion of wait state to ensure correct

synchronization of signals between the MCU subsystem and the DSP subsystem.

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