TMS320VC5470ZHKA datasheet(56/94 Pages) TI

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Electrical Specifications

December 2001 − Revised December 2002

SPRS017B

6.5.1 Divide-By-Two/Divide-By-Four Clock Option Timing

The frequency of the reference clock provided at the REFCLK pin can be divided by a factor of two or four

to generate the internal machine cycle. The selection of the clock mode is described in Section 3.4.7.

NOTE: The frequency injected must conform to specifications listed in Table 6−2.

Table 6−2 and Table 6−3 assume testing over recommended operating conditions and H = 0.5tc(CO)

(see Figure 6−2).

Table 6−2. Divide-By-Two/Divide-By-Four Clock Option Timing Requirements

MIN

MAX

UNIT

tc(CI)

Cycle time, REFCLK

†

tf(CI)

Fall time, REFCLK

tr(CI)

Rise time, REFCLK

tw(CIL)

Pulse duration, REFCLK low

tw(CIH) Pulse duration, REFCLK high

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies approaching

0 Hz.

Unless otherwise noted, the same switching characteristics that apply to DSP_CLKOUT also apply to

ARM_MCLK.

Table 6−3. Divide-By-Two/Divide-By-Four Clock Option Switching Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, DSP_CLKOUT

2tc(CI)

†

td(CIH-CO)

Delay time, REFCLK high to DSP_CLKOUT high/low

tf(CO)

Fall time, DSP_CLKOUT

tr(CO)

Rise time, DSP_CLKOUT

tw(COL)

Pulse duration, DSP_CLKOUT low

H−2

H + 2

tw(COH)

Pulse duration, DSP_CLKOUT high

H−2

H + 2

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies approaching

0 Hz.

tr(CO)

tf(CO)

DSP_CLKOUT

REFCLK

tw(COL)

td(CIH-CO)

tf(CI)

tr(CI)

tc(CO)

tc(CI)

tw(COH)

tw(CIH)

tw(CIL)

Figure 6−2. External Divide-by-Two Clock Timing

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