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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5470ZHKA датащи(PDF) 86 Page - Texas Instruments |
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TMS320VC5470ZHKA датащи(HTML) 86 Page - Texas Instruments |
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86 / 94 page  Electrical Specifications 77 December 2001 − Revised December 2002 SPRS017B The ARM SRAM read timing requirements listed in Table 6−35 represent back-to-back read operations to a zero-wait-state SRAM device. Table 6−35. ARM SRAM Timing Requirements (Read) MIN MAX UNIT 1 td(CSL-AV) Delay time, address valid from CS low − 3 4 ns 2 td(CSL−BHEV1) Delay time, byte enable high valid 1 from CS low − 3 4 ns 3 td(CSL-OEL) Delay time, output enable low from CS low − 3 4 ns 4 td(CSL-AIV1) Delay time, address invalid 1 from CS low E − 3† E + 4† ns 5 tw(CSL) Pulse duration, CS low 2E − 3.5† 2E + 3.5† ns 6 tsu(CSL-DV1) Setup time, data valid 1 from CS low E − 12† ns 7 td(CSL−AIV2) Delay time, address invalid 2 from CS low 2E − 3† 2E + 4† ns 8 th(CSL−DIV1) Hold time, data invalid 1 from CS low E − 1† ns 9 tsu(CSL−DV2) Setup time, data valid 2 from CS low 2E − 12† ns 10 td(CSL−BEIV1) Delay time, byte enable invalid 1 from CS low E − 4† E + 4† ns 11 td(CSL−BEV2) Delay time, byte enable valid 2 from CS low E − 2† E + 6† ns 12 th(CSL−DIV2) Hold time, data invalid 2 from CS low 2E − 1† ns 13 td(CSL−BEIV2) Delay time, byte enable invalid 2 from CS low 2E − 4† 2E + 4† ns 14 td(CSL−OEH) Delay time, output enable high from CS low 2E − 3† 2E + 4† ns † E = tw(ARM−R) |
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