AM85C30 datasheet(178/194 Pages) AMD

178 / 194 page

SCC Application Notes

AMD

7–29

ACD is asserted whenever the receiver detects line activity. This scheme is a significant

asset in the single bus (half-duplex) architecture shown in Figure 7–19. Consider the case

where Device 1 is transmitting and Device 4 is receiving. Although the message on the

bus is not read by Devices 2 and 3, their respective

ACD lines will be active (Low) due to

line activity at their receive inputs, RxL0 and RxL1. This prevents the controllers from

transmitting as long as there is line activity, thus avoiding any potential collisions or inter-

ruption of the transmission. During transmission,

ACD is internally negated. The ACD and

RTS gating scheme does not interfere with normal data transmission.

In this example (Figure 7–19), the Am7960 will generate and recognize its own preamble

because the Am8530H does not have that capability. This is called Mode 0 operation and

is accomplished by holding the Mode pin Low. The Master Reset input is an asynchro-

nous transceiver reset. When asserted, all interface signals will be inhibited with the ex-

ception of transmit clock. It has an internal pull-up resistor, internal discharge clamp

diode, and input hysteresis to provide power-on reset with a single external capacitor to

ground.

The Clear-To-Send (

CTS) is activated just before the Am7960 is ready to transmit data.

The interface for Transmit Data (TxD), Transmit Clock (TxC), Receive Data (RxD), and

Carrier Sense (

CS) between the Am7960 and the Am8530H are direct connections. This

ease of connection is possible because the Am8530 supports the modem-like interface

(standard for most USARTs and serial communications controllers) for which the Am7960

is designed.

The RxC rising edge to RxD valid time on the Am7960 varies from –5 ns to +20ns. The

Am8530H clocks in data on the rising edge of RxC and requires a set-up of at least 0 ns

from RxD to the rising edge of

RxC. This set-up time will not be met if the same RxC

edge that clocks out data from the Am7960 is used to clock in data to the Am8530H. This

problem can be solved by inverting the receive clock from the Am7960 before feeding it

into the Am8530H.

The X1 and X2 pins supply the clock to the digital phase-locked loop in the Am7960,

which in turn generates the TxC and RxC signals. These inputs can be driven by either a

crystal or a TTL source. The crystal oscillator circuit must be used, in 3rd harmonic, for

frequencies above 24 MHz. If a TTL source is connected to X1, the X2 pin must be left

open.

The hardware connections between the Am8530H and a CPU and DMA controller are

equally simple. Use of a DMA controller is suggested for any system that transmits above

500 kb/s, to simplify data transfers between the memory and the Am8530H. After initializ-

ing the Am8530H and the DMA channel, the CPU leaves the actual transfer of data to the

DMA controller (explained under Software Considerations later in this application note).

During transmission, the SCC requests a DMA transfer by pulling the

W/REQ line active

(Low) if the transmit buffer is empty, or keeps it High until the transmit buffer is empty.

Similarly, the receive section will request a DMA transfer if the receive buffer contains a

character or will keep

W/REQ High until a character enters the receive buffer. A flag

within the SCC can be read to recognize an End-Of-Message (EOM).

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