AM85C30 datasheet(163/194 Pages) AMD

163 / 194 page

SCC Application Notes

AMD

7–14

7.3.4

Interrupt Routine

When the SCC has been initialized and enabled, it is ready for communication. The trans-

mitter buffer and the receive FIFO are both empty. An interrupt will not be generated until

the software writes the first character to the transmit buffer. Once the first character is in

the SCC shift register, the first transmit interrupt will occur. The SCC then continues to

issue interrupts to the interrupt controller until the end of the message. At the end of the

message, a Reset Transmitter Interrupt Pending (WR0) is issued to clear the transmit

interrupt. After the last character is read into the SCC, the interrupts will cease until an-

other message is written into the transmitter.

Once an interrupt is received and the interrupt controller vectors to the interrupt routine,

RR2 is read from channel B. The value read from RR2 is the vector, including status. This

vector shows the status of the highest priority interrupt pending (IP) at the time it is read.

Once the highest priority interrupt condition is cleared, RR2 will show the status of the

next highest interrupt pending, if one is present. This allows multiple interrupts to be serv-

iced without the overhead of the interrupt acknowledge cycle of the interrupt controller.

MIE is disabled and then enabled to guarantee an edge for an edge-sensitive interrupt

controller.

The following example shows how the interrupt routine should be coded.

BEGIN:

INPUT

RR2

;Read RR2 from channel B

TEST

Bit 4

;Test for Tx Empty

TXEMPTY

;Jump to Transmit Routine

TEST

Bit 5

;Test for Rx full

JUMP

RXFULL

;Jump to Receive Routine

OUT

WR9 00

;MIE Disabled

OUT

EOI

;Output EOI to Interrupt Controller

IRET

;Return to Main

;

TXEMPTY:

TEST

NOMORE

;Test a last character flag

LAST

;Jump to LAST if no more characters

OUTPUT

CHAR

;Output character to data port

DEC

CHARCOUNT

;Decrement character count

JUMP

BEGIN

;Jump to BEGIN to test for more IP

;

LAST:

OUTPUT

RR0,28H

;Reset Tx Interrupt Pending

JUMP

BEGIN

;Jump to BEGIN to test for more IP

;

RXFULL:

INPUT

RR1

;Read RR1

COMPARE RR1,00

;Test for special condition bit set

JUMP

;Jump to SPECIAL

INPUT

CHAR

;Input charcater from data port

JUMP

BEGIN

;Jump to BEGIN to test for more IP

;

SPECIAL;

This means a framing error, receive overrun error or parity error

has occurred. Character may be read but data is not correct.

A flag should be set to post the error.

OUTPUT RR0, 30H

;Reset Error Command

JUMP BEGIN

;Jump to BEGIN to test for more IP

Figure 7–5. SCC Interrupt Routine

AM85C30 датащи(PDF) 163 Page - Advanced Micro Devices

AM85C30 датащи(HTML) 163 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL