AM85C30 datasheet(119/194 Pages) AMD

119 / 194 page

AMD

6–9

Receive Interrupt on Special Condition (11). This mode allows the receiver to interrupt

only on characters with a special receive condition. When an interrupt occurs, the data

containing the error are held in the receive FIFO until an Error Reset command is issued.

When using this mode in conjunction with a DMA, the DMA can be initialized and enabled

before any characters have been received by the SCC. This eliminates the time-critical

section of code required in the Receive Interrupt on First Character or Special Condition

mode; i.e., all data can be transferred via the DMA so that the CPU need not handle the

first received character as a special case.

Bit 2: Parity Is Special Condition

If this bit is set to ‘1’, any received characters with parity not matching the sense pro-

grammed in WR4 give rise to a Special Receive Condition. If parity is disabled (WR4),

this bit is ignored. A special condition modifies the status of the interrupt vector stored in

WR2. During an interrupt acknowledge cycle, this vector can be placed on the data bus.

Bit 1: Transmitter Interrupt Enable

If this bit is set to “1’, the transmitter requests an interrupt whenever the transmit buffer

becomes empty.

Bit 0: External/Status Master Interrupt Enable

This bit is the master enable for External/Status interrupts including

DCD, CTS, SYNC

pins, break/abort, the beginning of CRC transmission when the Transmit/Underrun/EOM

latch is set, or when the counter in the baud rate generator reaches ‘0’. Write Register 15

contains the individual enable bits for each of these sources of External/Status interrupts.

This bit is reset by a channel or hardware reset.

6.2.3

Write Register 2 (Interrupt Vector)

WR2 is the interrupt vector register. Only one vector register exists in the SCC, but it can

be accessed through either channel. The interrupt vector can be modified by status infor-

mation. This is controlled by the Vector Includes Status (VIS) and the Status High/Status

Low bits in WR9. When the register is accessed in Channel A, the vector returned is the

vector actually stored in WR2. When this register is accessed in Channel B, the vector

returned includes status information in bits 1, 2, and 3 or in bits 6, 5, and 4, depending on

the state of the Status High/Status Low bit in WR9 and independent of the state of VIS bit

in WR9. The bit positions for WR2 are shown in Figure 6–3.

D7 D6 D5 D4 D3 D2 D1 D0

Figure 6–3. Write Register 2

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