AM79C989 datasheet(18/37 Pages) AMD

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Am79C989

PRELIMINARY

Table 2.

QuEST Device Address Designations

Table 3.

Channel Address Designations

Interrupt Function

The Interrupt function indicates when there is a change

in the Link Status, Duplex Mode, Auto-Negotiation sta-

tus, MAU Error status, or any combination thereof for

any port. The Interrupt Register (Register 16) contains

the interrupt status and interrupt enable bits. The status

is always updated whether the interrupt enable bits are

set or not. However, if the interrupt enable bits are set

active, the logical OR of the selected bits will drive the

QINT open drain output pin.

When an interrupt occurs, the system will need to poll

the interrupt register to determine the source of the in-

terrupt and to clear the status bits. The individual regis-

ters can be read to determine the exact nature of the

change in status. Individual bits clear on read (COR)

except for the Jabber error, which is a Self-Clearing

(SC) bit when the QuEST device exits the Jabber state.

3.3 Volt Operation

The QuEST device is designed to easily and reliably in-

terface to systems with 3.3 V or 5 V power supplies.

This is accomplished by having a separate power sup-

ply pin, VDDIO, which can be connected to either a 3.3

V or 5 V supply. The only pins affected by the choice of

supply are: QRX_DATA, QRX_VALID, QRX_CRS,

QCLSN, and MDIO.

The data sheet speciﬁcation for the QuEST device is

for TTL input and output levels. The QuEST device

meets these speciﬁcations, regardless of which supply

voltage is used. The difference made by using a 3.3 V

supply is that the MAXIMUM output voltage on the pins

listed above is guaranteed by design not to exceed

3.3 V.

The QuEST device supports nine physical registers per

port plus four registers which are globally shared

among all four ports. In summary, there are 40 registers

available.

Table 4.

Shared Registers

Four registers are globally shared among all four ports:

Registers 2 and 3 designate the Device ID, Register 16

is Interrupt Enable and Status, and Register 17 is Sum-

mary Status. When accessing the shared registers, the

lower two bits of the PHYAD address (bits A1 and A0)

are ignored.

PHYAD Bits

Signals with Pull up Resistors

no signals

QCLSN

QRX_VALID

QRX_ VALID, QCLSN

QRX_DATA

QRX_DATA, QCLSN

QRX_DATA, QRX_ VALID

QRX_DATA, QRX_ VALID, QCLSN

PHYAD Bit

Channel Number

REGAD

PHYAD [0:1] /Port

Port Number

Auto Negotiation

Control

0123

Auto Negotiation

Status

0123

2-3

Device ID

Shared

Auto Negotiation

0123

Auto Negotiation Link

Partner

0123

Auto Negotiation

Expansion

0123

Auto Negotiation Next

Page

0123

8-15

Unused

Status Change

Interrupt

Shared

Summary Status

Shared

Control

0123

Status

0123

Error Mask

0123

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