AM79C989 datasheet(16/37 Pages) AMD

16 / 37 page

Am79C989

PRELIMINARY

Either ﬁve or six signal pins are used for the AUI func-

tion: DO

±, DI±, PCI/CI+; and, if Interrupt is disabled,

QINT/CI-.

AUI Transmitter

The AUI circuit provides a differential transmit circuit

which operates at Pseudo Emitter Coupled Logic

(PECL) levels. The DO

± circuit provides an internal ter-

mination resistor of 80.4

Ω. When the AUI port is dis-

abled, the DO driver circuit will idle at zero differential

voltage with an impedance of 80.4

Ω.

AUI Receiver

The AUI receive circuit consists of a PECL receiver cir-

cuit. It is recommended that DI

± inputs be terminated

differentially with two 40.2

Ω resistors with the middle

node connected to a 0.1 to 0.01

µF by-pass capacitor

to analog ground.

In order for the AUI to unsquelch, the differential re-

ceive data must exceed requirements for both negative

amplitude and time duration. Once unsquelched, the

receive data is sent to the Manchester decode unit for

clock recovery and data extraction.

Collision

The AUI collision front-end circuit is similar to the AUI

receiver circuit. The CI

± inputs should be differentially

terminated with two 40.2

Ω resistors with the middle

node of the resistors connected to a 0.1 to 0.01

µF by-

pass capacitor to analog ground. In order for a collision

to be detected, the differential receive data must pass

negative amplitude and time duration. Once the colli-

sion circuit is unsquelched, the collision is indicated on

the QCLSN signal during the port 0 multiplexed time

slot.

The AUI port can be conﬁgured as a full-duplex port for

10BASE-FL application. If conﬁgured as a full-duplex

port, the collision indication will not be signaled on the

QuASI Interface.

When the AUI and Interrupt modes are enabled, the

collision front end is changed to a single-ended input

with the same threshold requirements as above. The

positive signal of the collision differential pair is used as

the collision input. The CI- signal is isolated and biased

to an idle level. This frees up the external pin to be

switched in with the interrupt driver circuitry and to

function as an open drain interrupt output.

QuASI Interface

The QuASI interface provides four 10-Mbps Ethernet

channels that are serially multiplexed to a set of shared

pins. The data rate of these pins is four times faster

than a standard 10-Mbps serial interface.

The QuASI interface is composed of a clock, QRST/

STRB, and six signal pins. The purpose of this interface

is to allow time division multiplexing of the digital serial

data. The clock input, SCLK, is nominally a 40-MHz sig-

nal. This clock input should have a frequency tolerance

to 100 ppm.

The QuEST internally divides the 40-MHz SCLK input

into four clock phases or slots. (Refer to QuASI inter-

face diagram in the

Switching Characteristics section.)

When the QRST/STRB signal is de-asserted, the inter-

nal divide circuit is locked into a repeatable sequence.

The ﬁrst rising edge of the SCLK input after the

de-assertion of QRST/STRB results in the input sig-

nals, QTX_EN and QTX_DATA, being locked to chan-

nel 0. To transmit data for the ﬁrst channel 0 slot, the

transmit data and transmit enable signal must meet the

setup and hold times associated with the ﬁrst rising

edge of SCLK after QRST/STRB is driven inactive.

The repetitive channel order for transmitting data is

channel 0 to channel 3.

The second rising edge of the SCLK input after reset

de-assertion results in the output signals, QRX_DATA,

QRX_VALID, QRX_CRS, and QCLSN, being locked to

channel 3. The receive data for the ﬁrst channel 3 slot

is valid during the second rising edge of SCLK. Suc-

cessive clock edges increment the channel slot number

in a repetitive fashion. The repetitive channel order is

channel 0 to channel 3. Consequently, all signal pins

are synchronous to the clock pin, SCLK.

The STRB (strobe) function of the QRST/STRB input

pin allows the option to strobe the input for a single

clock during normal operation to ensure alignment of

the QuASI interface to channel 0. The use of the strobe

option minimizes possibility of channel misalignments.

In order to transmit a packet, QTX_EN needs to be

asserted during the correct channel or slot number. If

QTX_EN is asserted, then the NRZ QTX_DATA is inter-

preted and sent to the Manchester encode unit for

transmission to the 10BASE-T or AUI interface.

QTX_EN and QTX_DATA should contain the preamble

and data portions of the frame to be sent. The End of

Transmission Delimiter will be added by the encode

unit. As an example, if channel 0 is the only transmit

channel active, then QTX_EN signal will only be as-

serted during the slot time of channel 0. As part of the

transmission process, the QTX_DATA data signal is

looped back to the QRX_CRS and QRX_VALID signals

when in half-duplex mode and the Link Pass State.

When data is received from the network, the data is ﬁrst

placed in the Elasticity FIFO. There are three signals

associated with the receive stream: QRX_CRS,

QRX_VALID, and QRX_DATA. When receive data trig-

gers the squelch paths of either the 10BASE-T or AUI

receiver, the QRX_CRS signal is asserted at the earli-

est possible time. Receive Carrier Sense (QRX_CRS)

signal is used for signaling real-time network activity to

the external device connected to the QuEST device.

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