AM79C989 datasheet(17/37 Pages) AMD

17 / 37 page

Am79C989

PRELIMINARY

QRX_CRS signal is primarily useful for calibrating net-

work timers in the external MAC or repeater device.

Data which is held in the elasticity FIFO will be delayed.

When the QRX_VALID (Receive Data Valid) is

asserted in the appropriate slot, the QRX_DATA is

valid. QRX_VALID is used as a framing signal to indi-

cate when the QRX_DATA is valid. QRX_VALID and

QRX_DATA will lag QRX_CRS by up to four bit times

(400 ns) in the beginning of the frame and up to 8 bits

by the end of the frame. The reason that QRX_VALID

lags QRX_CRS signal by a variable amount of time is

due to the inherent rate mismatch between the

received data and network clocks.

The QCLSN signal is asserted whenever a network

collision is detected. QCLSN is time multiplexed like the

other receive signals. QCLSN has a speciﬁc meaning

within the speciﬁed channel or slot number. Collision

indication is asserted in its appropriate time slot when-

ever a network collision is detected. The QCLSN pin

may be optionally asserted if the SQE_TEST disable

bit, Control Register (Reg. 18, bit 0), is in a cleared

state after transmission of a packet.

In summary, the QuASI Interface is synchronous to the

clock input, SCLK. A reset signal, QRST/STRB, is pro-

vided which serves two purposes, hardware reset and

a means for channel slot synchronization. There are six

additional signal pins that communicate the serial data

to and from the QuEST device.

Management Interface

The QuEST device incorporates a two-wire Manage-

ment Interface in conformance with the MII Manage-

ment Interface of the IEEE 802.3u Standard. The

interface includes a management clock, MDC, and a

serial data I/O pin, MDIO. The Management Interface

clock can operate as high as 20 MHz; there is no lower

frequency limit. The MDIO signal serves as both con-

trol and data. The ﬁrst part of the command is com-

posed of control information, while the second half is

composed of data. The management frame format is

indicated below.

Table 1.

Management Frame Fields

The Management Frame

The management frame begins with the Start of Frame

(ST) delimiter indicated by a <01> pattern. After the ST

pattern, the Operation Code (OP) indicates either a

read or a write, followed by the PHYAD and REGAD

ﬁelds. The speciﬁc address is identiﬁed by the ﬁve bits

of the PHY address (PHYAD); the speciﬁc register is

identiﬁed by the ﬁve bits of the Register Address (RE-

GAD). The Turn Around (TA) ﬁeld follows and provides

a two-cycle delay for redirecting the MDIO bus during

read commands, to avoid signal contention. The man-

agement frame includes the 16-bit wide data ﬁeld and

terminates with an idle state indication.

PHY Addressing

PHYAD is the unique address of any PHY connected to

this Serial Management Interface. Each QuEST sup-

ports four PHYs, and up to eight QuEST devices can

be connected to the Management Interface. A total of

32 PHYs can be managed. (Refer to Table 2.)

The internal QuEST address is formed through exter-

nal means. During reset, the QRX_DATA, QRX_VALID,

QRX_CRS, and QCLSN signals of the QuEST device

are in tristate. At the rising edge of reset, the QuEST

device latches signal pins QRX_VALID, QRX_CRS,

and QCLSN to form the internal address which the

QuEST device will use to match against. The QuEST

device provides internal pull-down resistors of approxi-

mately 100 k

Ω.

Pull-up resistors of 10 k

Ω in value can be placed on the

QRX_DATA, QRX_VALID, and QCLSN signals to de-

ﬁne the internally latched address. The internal latch

address is shown below. The internally latched address

must be unique among QuEST devices shared by a

single Management Interface. To form the QuEST ad-

dress “000,” no resistors need to be connected. To form

the QuEST address “101”, external pull-up resistors

are required to be added to the QRX_DATA and

QCLSN signals, and so forth.

A speciﬁc PHY address (PHYAD) is formed with ﬁve

bits. The upper three bits of the PHYAD, A4, A3, and

A2, are matched to an internal QuEST device address

which acts as a chip selection function. Setting each of

these three bits to 0 or 1 in combination allows speciﬁc

designation of up to eight QuEST devices. The lower

two bits of the PHYAD designate the channel number

of the designated QuEST device.

PHYAD

REGAD

DATA

IDLE

READ

A4AAAA0

R4RRRR0

D15DDDDDDDDDDDDDDD0

WRITE

A4AAAA0

R4RRRR0

D15DDDDDDDDDDDDDDD0

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