AM79C976 datasheet(180/309 Pages) AMD

180 / 309 page

180

Am79C976

8/01/00

P R E L I M INARY

EXDINTE

Obsolete function. Writing has no

effect. Read as undefined.

MPPLBA

Magic Packet Physical Logical

Broadcast Accept. If MPPLBA is

at its default value of 0, the

Am79C976 controller will only de-

tect a Magic Packet frame if the

destination address of the packet

matches the content of the physi-

cal address register (PADR). If

MPPLBA is set to 1, the destina-

tion address of the Magic Packet

frame can be unicast, multicast,

or broadcast. Note that the set-

ting of MPPLBA only affects the

address detection of the Magic

Packet frame. The Magic Packet

frame’s data sequence must be

made up of 16 consecutive phys-

ical addresses (PADR[47:0]) re-

gardless

what

kind

destination address it has. This

bit is OR’ed with EMPPLBA bit

(CSR116, bit 6).

Read/Write accessible. MPPLBA

is set to 0 by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

MPINT

Magic Packet Interrupt. Magic

Packet Interrupt is set by the

Am79C976 controller when the

device is in the Magic Packet

mode and the Am79C976 con-

troller receives a Magic Packet

frame. When MPINT is set to 1,

INTA is asserted if IENA (CSR0,

bit 6) and the enable bit MPINTE

are set to 1.

Read/Write accessible. MPINT is

cleared by the host by writing a 1.

Writing a 0 has no affect. MPINT

cleared

H_RESET,

S_RESET, or by setting the

STOP bit.

MPINTE

Magic Packet Interrupt Enable. If

MPINTE is set to 1, the MPINT bit

will be able to set the INTR bit.

Read/Write accessible. MPINTE

is cleared to 0 by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

MPEN

Magic Packet Enable. MPEN al-

lows activation of the Magic

Packet mode by the host. The

Am79C976 controller will enter

the Magic Packet mode when

both MPEN and MPMODE are

set to 1.

Read/Write accessible. MPEN is

cleared to 0 by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

MPMODE

The Am79C976 controller will en-

ter the Magic Packet mode when

MPMODE is set to 1 and either

PG is asserted or MPEN is set

to 1.

Read/Write

accessible.

MP-

MODE

cleared

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

SPND

Suspend. Setting SPND to 1 will

cause the Am79C976 controller

to start requesting entrance into

suspend mode. The host must

poll SPND until it reads back 1 to

determine that the Am79C976

controller has entered the sus-

pend mode. Setting SPND to 0

will get the Am79C976 controller

out of suspend mode. SPND can

only be set to 1 if STOP (CSR0,

bit 2) is set to 0. H_RESET,

S_RESET or setting the STOP bit

will get the Am79C976 controller

out of suspend mode.

Requesting entrance into the

suspend mode by the host de-

pends on the setting of the

FASTSPNDE bit (CSR7, bit 15).

Refer to the bit description of the

FASTSPNDE bit and the Sus-

pend section in Detailed Func-

tions, Buffer Management Unit

for details.

In suspend mode, all of the CSR

and BCR registers are accessi-

ble. As long as the Am79C976

controller is not reset while in

suspend mode (by H_RESET,

S_RESET or by setting the STOP

bit), no re-initialization of the de-

vice is required after the device

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