AM79C976 datasheet(177/309 Pages) AMD

177 / 309 page

8/01/00

Am79C976

177

P R E L I M INARY

generated when the header bytes

have been written to the header

memory area.

Read/Write accessible. The LAP-

PEN bit will be reset to 0 by

H_RESET or S_RESET and will

be unaffected by STOP.

See Appendix B for more infor-

mation on the Look Ahead Pack-

et Processing concept.

DXMT2PD

Disable Transmit Two Part Defer-

ral (see Medium Allocation sec-

tion

the

Media

Access

Management section for more

details). If DXMT2PD is set,

Transmit Two Part Deferral will

be disabled.

Read/Write

accessible.

DXMT2PD

cleared

H_RESET or S_RESET and is

not affected by STOP.

EMBA

Enable Modified Back-off Algo-

rithm (see Contention Resolution

section in Media Access Man-

agement section for more de-

tails). If EMBA is set, a modified

back-off algorithm is implement-

ed.

Read/Write accessible. EMBA is

cleared

H_RESET

S_RESET and is not affected by

STOP.

BSWP

Byte Swap. This bit is used to

choose between big and little En-

dian modes of operation. When

BSWP is set to a 1, big Endian

mode is selected. When BSWP is

set to 0, little Endian mode is se-

lected.

When big Endian mode is select-

ed, the Am79C976 controller will

swap the order of bytes on the AD

bus during a data phase on ac-

cesses to the FIFOs only. Specif-

ically, AD[31:24] becomes Byte

0, AD[23:16] becomes Byte 1,

AD[15:8] becomes Byte 2, and

AD[7:0] becomes Byte 3 when

big Endian mode is selected.

When little Endian mode is se-

lected, the order of bytes on the

AD bus during a data phase is:

AD[31:24] is Byte 3, AD[23:16] is

Byte 2, AD[15:8] is Byte 1, and

AD[7:0] is Byte 0.

Byte swap only affects data

transfers that involve the FIFOs.

Initialization block transfers are

not affected by the setting of the

BSWP bit. Descriptor transfers

are not affected by the setting of

the BSWP bit. RDP, RAP, BDP

and PCI configuration space ac-

cesses are not affected by the

setting of the BSWP bit. Address

PROM transfers are not affected

by the setting of the BSWP bit.

Expansion ROM accesses are

not affected by the setting of the

BSWP bit.

Note that the byte ordering of the

PCI bus is defined to be little En-

dian. BSWP should not be set to

1 when the Am79C976 controller

is used in a PCI bus application.

Read/Write accessible. BSWP is

cleared

H_RESET

S_RESET and is not affected by

STOP.

1-0

RES

Reserved locations. The values

written to these bits have no ef-

fect on the operation of the de-

vice. These bits should be read

as undefined.

&657HVWDQG)HDWXUHV &RQWURO

Certain bits in CSR4 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR4 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

RES

Reserved location. The value

written to this bit has no effect on

the operation of the device. This

bit should be read as undefined.

DMAPLUS

Writing and reading from this bit

has no effect. DMAPLUS is al-

ways 0.

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