AM79C976 datasheet(183/309 Pages) AMD

183 / 309 page

8/01/00

Am79C976

183

P R E L I M INARY

is not affected by S_RESET or

setting the STOP bit.

MAPINTE

MII Auto-Poll Interrupt Enable. If

MAPINTE is set, the MAPINT bit

will be able to set the INTR bit.

Read/Write accessible.

MAP-

INTE is set to 0 by H_RESET and

is not affected by S_RESET or

setting the STOP bit

MCCINT

MII

Management

Command

Complete Interrupt. The MII Man-

agement Command Complete In-

terrupt is set by the Am79C976

controller when a read or write

operation to the MII Data Port

(BCR34) is complete.

When MCCINT is set to 1, INTA

is asserted if the enable bit

MCCINTE is set to 1.

Read/Write accessible. MCCINT

is cleared by the host by writing a

1. Writing a 0 has no effect.

MCCINT is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

MCCINTE

MII

Management

Command

Complete Interrupt Enable. If

MCCINTE

set

the

MCCINT bit will be able to set the

INTR bit when the host reads or

writes to the MII Data Port

(BCR34) only. Internal MII Man-

agement Commands will not gen-

erate an interrupt. For instance,

Auto-Poll state machine generat-

ed MII management frames will

not generate an interrupt upon

completion unless there is a com-

pare error which gets reported

through the MAPINT (CSR7, bit

6) interrupt or the MCCIINTE is

set to 1.

Read/Write

accessible.

MC-

CINTE is set to 0 by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

MCCIINT

MII

Management

Command

Complete Internal Interrupt. The

MII

Management

Command

Complete Interrupt is set by the

Am79C976 controller when a

read or write operation on the MII

management port is complete

from an internal operation. Exam-

ples of internal operations are

Auto-Poll or MII Management

Port generated MII management

frames. These are normally hid-

den to the host.

When MCCIINT is set to 1, INTA

is asserted if the enable bit

MCCINTE is set to 1.

Read/Write accessible. MCCIINT

is cleared by the host by writing a

1. Writing a 0 has no effect.

MCCIINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MCCIINTE

MII

Management

Command

Complete Internal Interrupt En-

able. If MCCIINTE is set to 1, the

MCCIINT bit will be able to set

the INTR bit when the internal

state

machines

generate

MII

management

frames.

For

in-

stance, when MCCIINTE is set to

1 and the Auto-Poll state ma-

chine generates a MII manage-

ment frame, the MCCIINT will set

the INTR bit upon completion of

the MII management frame re-

gardless of the comparison out-

come.

Read/Write

accessible.

MCCIINTE

set

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MIIPDTINT MII PHY Detect Transition Inter-

rupt. The MII PHY Detect Transi-

tion

Interrupt

set

the

Am79C976 controller whenever

the MIIPD bit (BCR32, bit 14)

transitions from 0 to 1 or vice ver-

sa.

Read/Write

accessible.

MIIP-

DTINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. MIIPDTINT is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

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