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AM79C976 датащи(PDF) 178 Page - Advanced Micro Devices

номер детали AM79C976
подробное описание детали  PCnet-PRO??10/100 Mbps PCI Ethernet Controller
PDF  309 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C976 датащи(HTML) 178 Page - Advanced Micro Devices

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178
Am79C976
8/01/00
P R E L I M INARY
13
RES
Reserved Location. Written as
zero and read as undefined.
12
TXDPOLL
Disable Transmit Polling. If TXD-
POLL is set, the Buffer Manage-
ment Unit will disable transmit
polling. Likewise, if TXDPOLL is
cleared, automatic transmit poll-
ing is enabled. If TXDPOLL is set,
TDMD bit in CSR0 must be set in
order to initiate a manual poll of a
transmit descriptor. Transmit de-
scriptor polling will not take place
if TXON is reset. Transmit polling
will take place following Receive
activities.
Read/Write
accessible.
TXD-
POLL is cleared by H_RESET or
S_RESET and is unaffected by
the STOP bit.
11
APAD_XMT Auto Pad Transmit. When set,
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes including FCS.
The FCS is calculated for the en-
tire frame, including pad, and ap-
pended after the pad field. When
the auto padding logic modifies a
frame, a valid FCS field will be
appended to the frame, regard-
less of the state of the DXMTFCS
bit (CSR15, bit 3) and of the
ADD_FCS bit in the transmit de-
scriptor.
Read/Write
accessible.
APAD_XMT
is
cleared
by
H_RESET or S_RESET and is
unaffected by the STOP bit.
10
ASTRP_RCVAuto Strip Receive. When set,
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
Read/Write
accessible.
ASTRP_RCV
is
cleared
by
H_RESET or S_RESET and is
unaffected by the STOP bit.
9
MFCO
Obsolete function. Writing has no
effect. Read as undefined.
8
MFCOM
Obsolete function. Writing has no
effect. Read as undefined.
7
UINTCMD
User
Interrupt
Command.
UINTCMD can be used by the
host to generate an interrupt un
related to any network activity.
Writing a 1 to this bit causes
UINT to be set to 1, which in turn
causes INTA to be asserted if in-
terrupts are enabled.
Read/Write accessible. UINTC-
MD is always read as 0.
6
UINT
User Interrupt. UINT is set by the
Am79C976 controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to 1.
Read/Write accessible. UINT is
cleared by the host by writing a 1.
Writing a 0 has no effect. UINT is
cleared
by
H_RESET
or
S_RESET or by setting the STOP
bit.
5
RCVCCO
Obsolete function. Writing has no
effect. Read as undefined.
4
RCVCCOM Obsolete function. Writing has no
effect. Read as undefined.
3
TXSTRT
Transmit Start status is set by the
Am79C976 controller whenever it
begins transmission of a frame.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
Read/Write accessible. TXSTRT
is cleared by the host by writing a
1. Writing a 0 has no effect. TX-
STRT is cleared by H_RESET,
S_RESET, or by setting the
STOP bit.
2
TXSTRTM
Transmit
Start
Mask.
If
TX-
STRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
Read/Write
accessible.
TX-
STRTM is set to 1 by H_RESET
or S_RESET and is not affected
by the STOP bit.



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