AM79C976 datasheet(184/309 Pages) AMD

184 / 309 page

184

Am79C976

8/01/00

P R E L I M INARY

MIIPDTINTEMII PHY Detect Transition Inter-

rupt Enable. If MIIPDTINTE is set

to 1, the MIIPDTINT bit will be

able to set the INTR bit.

Read/Write

accessible.

MIIP-

DTINTE is set to 0 by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

&65/RJLFDO $GGUHVV )LOWHU

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

LADRF[15:0]

Logical

Address

Filter,

LADRF-[15:0]. The content of this

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write

accessible.

These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

&65/RJLFDO $GGUHVV )LOWHU

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

LADRF[31:16]

Logical Address Filter, LADRF-

[31:16]. The content of this regis-

ter is undefined until loaded from

the initialization block after the

INIT bit in CSR0 has been set or

a direct register write has been

performed on this register.

Read/Write

accessible.

These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

&65/RJLFDO$GGUHVV)LOWHU

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

LADRF[47:32]Logical

Address

Filter,

LADRF[47:32]. The content of

this register is undefined until

loaded

from

the

initialization

block after the INIT bit in CSR0

has been set or a direct register

write has been performed on this

Read/Write

accessible.

These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

&65 /RJLFDO$GGUHVV )LOWHU

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

LADRF[63:48]

Logical

Address

Filter,

LADRF[63:48]. The content of

this register is undefined until

loaded

from

the

initialization

block after the INIT bit in CSR0

has been set or a direct register

write has been performed on this

Read/Write

accessible.

These

bits are cleared by H_RESET but

are unaffected by S_RESET, or

STOP.

&653K\VLFDO$GGUHVV 5HJLVWHU

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

PADR[15:0] Physical

Address

PADR[15:0]. The contents of this

are

loaded

from

EEPROM after H_RESET or by

EEPROM

read

command

(PREAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

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