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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C976 датащи(PDF) 179 Page - Advanced Micro Devices |
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AM79C976 датащи(HTML) 179 Page - Advanced Micro Devices |
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179 / 309 page  8/01/00 Am79C976 179 P R E L I M INARY 1-0 RES Reserved locations. Written as zeros and read as undefined. &65 ([WHQGHG &RQWURODQG,QWHUUXSW Certain bits in CSR5 indicate the cause of an interrupt. The register is designed so that these indicator bits are cleared by writing ones to those bit locations. This means that the software can read CSR5 and write back the value just read to clear the interrupt condition. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15 TOKINTD Obsolete function. Writing has no effect. Read as undefined. 14 LTINTEN Last Transmit Interrupt Enable. When this bit is set to 1, the LTINT bit in transmit descriptors can be used to determine when transmit interrupts occur. The Transmit Interrupt (TINT) bit will be set after a frame has been copied to the Transmit FIFO if the LTINT bit in the frame’s last transmit descriptor is set. If the LTINT bit in the frame’s last de- scriptor is 0 TINT will not be set after the frame has been copied to the Transmit FIFO. Read/Write accessible. LTINTEN is cleared by H_RESET or S_RESET and is unaffected by STOP. 13 TXDNINT Transmission Done Interrupt. This bit is set when the transmit- ter has finished sending a frame. This bit is included for debugging purposes. Read/Write accessible. TXDN- INT is cleared by the host by writ- ing a 1. Writing a 0 has no effect. The state of TXDNINT is not af- fected by clearing any of the PCI Status register bits that get set when a data parity error (DATAPERR, bit 8), master abort (RMABORT, bit 13), or target abort (RTABORT, bit 12) occurs. TXDNINT is cleared by H_RESET, S_RESET, or by set- ting the STOP bit. 12 TXDNINTEN Transmission Done Interrupt En- able. When this bit is set, the INTR bit will be set when the TXDNINT bit in INT0 is set. Read/Write accessible. TXDN- INTEN is cleared by H_RESET or S_RESET and is unaffected by STOP. 11 SINT System Interrupt is set by the Am79C976 controller when it de- tects a system error during a bus master transfer on the PCI bus. System errors are data parity er- ror, master abort, or a target abort. The setting of SINT due to data parity error is not dependent on the setting of PERREN (PCI Command register, bit 6). When SINT is set, INTA is assert- ed if the enable bit SINTE is 1. Note that the assertion of an in- terrupt due to SINT is not depen- dent on the state of the INEA bit, since INEA is cleared by the STOP reset generated by the system error. Read/Write accessible. SINT is cleared by the host by writing a 1. Writing a 0 has no effect. The state of SINT is not affected by clearing any of the PCI Status register bits that get set when a data parity error (DATAPERR, bit 8), master abort (RMABORT, bit 13), or target abort (RTABORT, bit 12) occurs. SINT is cleared by H_RESET or S_RESET and is not affected by setting the STOP bit. 10 SINTE System Interrupt Enable. If SIN- TE is set, the SINT bit will be able to set the INTR bit. Read/Write accessible. SINTE is set to 0 by H_RESET or S_RESET and is not affected by setting the STOP bit. 9-8 RES Reserved locations. Written as zeros and read as undefined. 7 EXDINT Obsolete function. Writing has no effect. Read as undefined. |
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