AM79C976 datasheet(169/309 Pages) AMD

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8/01/00

Am79C976

169

P R E L I M INARY

Software Timer Value Register

Offset 0D8h

The contents of this register are set to the default value

(0FFFFh) when the RST pin is asserted. This register

is not affected by the serial EEPROM read operation or

by a serial EEPROM read error.

Table 79. Software Timer Value Register

LINK_STAT

Link Status. This bit is set to the value of the Link Status bit in the status register (R1) of the default

external PHY. (The default external PHY is the PHY addressed by the AP_PHY0_ADDR field of

the AUTOPOLL0 Register.) This bit is updated each time the external PHY’s status register is read,

either by the Auto-Poll State Machine, by the Network Port Manager, or by a CPU-initiated read.

However, when the Force Link Status bit in CMD3 is set to 1, this bit is forced to 1, regardless of

the contents of the external PHY’s status register.

This bit is read only and is cleared by H_RESET.

AUTONEG_

COMPLETE

Auto-negotiation Complete. This bit is set to the value of the Auto-Negotiation Complete bit in

This bit is read only and is cleared by H_RESET.

MIIPD

MII PHY Detect. MIIPD reflects the quiescent state of the MDIO pin. MIIPD is continuously updated

whenever there is no management operation in progress on the MII interface. When a

management operation begins on the interface, the state of MIIPD is preserved until the operation

ends, when the quiescent state is again monitored and continuously updates the MIIPD bit. When

the MDIO pin is at a quiescent LOW state, MIIPD is cleared to 0. When the MDIO pin is at a

quiescent HIGH state, MIIPD is set to 1. Any transition on the MIIPD bit will set the MIIPDTINT bit

in INT0.

This bit is an alias of BCR32, bit 14.

This bit is read only and is cleared by H_RESET.

RX_

SUSPENDED

Receiver Suspended. This bit has the value 1 while the receiver is suspended, and it has the value

0 when the receiver is not suspended.

This bit is read only and is cleared by H_RESET.

TX_

SUSPENDED

Transmitter Suspended. This bit has the value 1 while the transmitter is suspended, and it has the

value 0 when the transmitter is not suspended.

This bit is read only and is cleared by H_RESET.

RUNNING

This bit is a read-only alias of the RUN bit in CMD0. When this bit is set, the device is enabled to

transmit and receive frames and process descriptors. Note that even though RUNNING is set, the

receiver or transmitter might be disabled because RX_SPND or TX_SPND is set (in CMD0).

This bit is read only and is cleared by H_RESET.

Bit

Name

Description

Bit

Name

Description

15-0

STVAL

Software Timer Value. STVAL controls the maximum time for the Software Timer to count before

generating the STINT (CSR7, bit 11) interrupt. The Software Timer is a free-running timer that is

started upon the first write to STVAL. After the first write, the Software Timer will continually count

and set the STINT interrupt at the STVAL period.

The STVAL value is interpreted as an unsigned number with a resolution of 10.24µs. For instance,

if STVAL is set to 48,828 (0BEBCh), the Software Timer period will be 0.5 s. The default value

(0FFFFh) corresponds to 0.6710784 s.

Setting STVAL to a value of 0 will result in erratic behavior.

This register is an alias of BCR31.

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