AM79C976 datasheet(157/309 Pages) AMD

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8/01/00

Am79C976

157

P R E L I M INARY

IPG: Inter-Packet Gap Register

Offset 18Dh

The contents of this register are set to 60h when the

RST pin is asserted, before the serial EEPROM is

read, and after a serial EEPROM read error.

Table 61. IPG: Inter-Packet Gap Register

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Offset 168h

The contents of this register are cleared to 0 when the

RST pin is asserted. This register is not cleared by the

serial EEPROM read operation or by a serial EEPROM

read error.

Table 62. Logical Address Filter Register

Bit

Name

Description

7-0

IPG

Inter Packet Gap. This value indicates the minimum number of network bit times after the end of a

frame that the transmitter will wait before it starts transmitting another frame. In half-duplex mode

the end of the frame is determined by CRS, while in full-duplex mode the end of the frame is

determined by TX_EN. The IPG value can be adjusted to compensate for delays through the

external PHY device.

IPG should be programmed to the nearest nibble. The two least significant bits are ignored. For

example, programming IPG to 63h has the same effect as programming it to 60h.

CAUTION: Use this parameter with care. By lowering the IPG below the IEEE 802.3 standard 96

bit times, the Am79C976 controller can interrupt normal network behavior.

This register is an alias for CSR125, bits [15:8].

Bit

Name

Description

63-0

LADRF

Logical Address Filter, LADRF[63:0]. This register contains a 64-bit mask that is used to accept

incoming logical (or multicast) addresses. If the first bit in the incoming address (as transmitted on

the wire) is a 1, the destination address is a logical address.

A logical address is passed through the CRC generator to produce a 32-bit result. The high order

6 bits of this result are used to select one of the 64-bit positions in the Logical Address Filter. If the

selected filter bit is set, the address is accepted, and the frame is copied into host system memory.

The Logical Address Filter is used in multicast addressing schemes. The acceptance of the

incoming frame based on the filter value indicates that the message may be intended for the node.

It is the responsibility of the host CPU to compare the destination address of the stored message

with a list of acceptable multicast addresses to determine whether or not the message is actually

intended for the node.

The contents of this register should be loaded from EEPROM. This register can also be loaded

from the initialization block after the INIT bit in CSR0 has been set. This register is an alias for

CSR8, CSR9, CSR10, and CSR11.

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