AM79C970A datasheet(148/219 Pages) AMD

148 / 219 page

AMD

P R E L I M I N A R Y

148

Am79C970A

transmission for the purpose of

SQE testing will not cause the

LEDOUT bit to be set.

Read/Write accessible always.

COLE is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

BCR6: LED2 Status

Bit

Name

Description

BCR6 determines which func-

tion(s) activate the

LED2 pin. The

pin will indicate the logical OR of

the enabled functions. BCR6 de-

faults to Receive Polarity Status

(RXPOL) with pulse stretcher

enabled (PSE = 1).

Note that bits 15–0 in this register

are programmable through the

external EEPROM. Reserved

bits and read-only bits should be

programmed to ZERO.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

LEDOUT

This bit indicates the current

(non-stretched) value of the LED

output pin. A value of ONE in this

bit indicates that the OR of the

enabled signals is true.

The logical value of the LEDOUT

status signal is determined by the

settings of the individual Status

Enable bits of this register (bits 8

and 6–0).

Read accessible always. This bit

is read only. Writes have no ef-

fect. LEDOUT is unaffected by

H_RESET, S_RESET or by set-

ting the STOP bit.

LEDPOL

LED Polarity. When this bit has

the value ZERO, the LED pin will

be asserted LOW whenever the

OR of the enabled signals is true,

and the LED pin will be disabled

and allowed to float whenever

the OR of the enabled signals is

false. (The LED output will be an

open drain output, and the output

value will be the inverse of the

LEDOUT status bit.)

When this bit has the value ONE,

the LED pin will be asserted

HIGH whenever the OR of the

enabled signals is true, and the

LED pin will be driven to a LOW

level whenever the OR of the en-

abled signals is false. (The LED

output will be a totem pole output,

and the output value will be the

same polarity as the LEDOUT

status bit.)

The setting of this bit will not ef-

fect the polarity of the LEDOUT

bit for this register.

Read/Write accessible always.

LEDPOL is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

LEDDIS

LED Disable. This bit is used to

disable the LED output. When

LEDDIS is set to ONE and

LEDPOL is cleared to ZERO, the

LED output pin will be floating.

When LEDDIS is set to ONE and

LEDPOL is set to ONE, the LED

output pin will be driven LOW.

When LEDDIS has the value

ZERO, the LED output value will

be governed by the LEDOUT and

LEDPOL values.

Read/Write accessible always.

LEDDIS is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

12–10

RES

Reserved locations. Written as

ZEROs and read as undefined.

MPSE

Magic Packet Status Enable.

When this bit is set to ONE, a

value of ONE is passed to the

LEDOUT bit in this register when

magic packet mode is enabled

and a magic packet is detected

on the network.

Read/Write accessible always.

MPSE is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

FDLSE

Full-duplex Link Status Enable.

Indicates the full-duplex Link

Test Status. When this bit is set

to ONE, a value of ONE is

passed to the LEDOUT signal

when the PCnet-PCI II controller

is functioning in a Link Pass state

and full-duplex operation is en-

abled. When the PCnet-PCI II

controller is not functioning in a

Link Pass state with full-duplex

operation being enabled, a value

of ZERO is passed to the

LEDOUT signal.

When the 10BASE-T port is ac-

tive, a value of ONE is passed to

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