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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IC-HT датащи(PDF) 40 Page - IC-Haus GmbH |
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IC-HT датащи(HTML) 40 Page - IC-Haus GmbH |
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40 / 42 page  prel imin ary prel imin ary iC-HT DUAL CW LASER DIODE DRIVER Rev A1, Page 40/42 Channel 2 configuration registers EACC2 Addr. 0x15; bit 0 R/W 0 0 APC mode enabled for channel 2 (light power regulation) 1 ACC mode enabled for channel 2 (laser current regulation) Table 102: Enable APC/ACC channel 2 ECIE2 Addr. 0x15; bit 1 R/W 0 0 External CI capacitor for channel 2 disconnected 1 External CI capacitor for channel 2 connected Table 103: Enable external CI capacitor channel 2 DISP2 Addr. 0x15; bit 2 R/W 0 0 Internal resistor at MDA2 enabled for channel 2 1 Internal resistor at MDA2 disabled for channel 2 Table 104: Disable PLR channel 2 DISC2 Addr. 0x15; bit 3 R/W 1 0 Channel 2 can be enabled by EC2 pin 1 Channel 2 cannot be enabled by EC2 pin Table 105: Disable channel 2 EOC2 Addr. 0x15; bit 4 R/W 1 0 Channel 2 regulator offset compensation disabled 1 Channel 2 regulator offset compensation enabled Table 106: Enable offset compensation channel 2 ADCC2(2:0) Addr. 0x15; bit 7:5 R/W 000 0xx Channel 2 ADC disabled 100 Channel 2 ADC sourced by V(MDA2), ADSNF2 = 0 100 Channel 2 ADC sourced by V(PLR2), ADSNF2 = 1 101 Channel 2 ADC sourced by V(VB) 110 Channel 2 ADC sourced by V(VDD) 111 Channel 2 ADC sourced by V(LDK2) Table 107: ADC source selection channel 2 ILIM2 Addr. 0x16; bit 7:0 R/W 0xFF 0x00 Channel 2 overcurrent threshold set to the minimum current . . . Channel 2 overcurrent threshold set to Ilim = (∆ I(LDK ) · n), n from 0 to 255 0xFF Channel 2 overcurrent threshold set to the maximum current Table 108: Overcurrent threshold configuration chan- nel 2 RMD2 Addr. 0x17; bit 7:0 R/W 0xFF 0x00 PLR2 resistor set to the minimum resistance . . . PLR2 resistor set to Rmd = Rmd0(1 + ∆ Rmd (%) 100 )n+1, n from 0 to 255 0xFF PLR2 resistor set to the maximum resistance Table 109: MDA resistor channel 2 COMP2 Addr. 0x18; bit 6:4 R/W 011 000 Minimum compensation current for the channel 2 regulator, slower response . . . 111 Maximum compensation current for the channel 2 regulator, faster response Table 110: Current compensation channel 2 RLDKS2 Addr. 0x18; bit 3:2 R/W 00 00 V(LDK2) < 0.5 V sets the LDKSAT2 alarm bit 01 V(LDK2) < 0.8 V sets the LDKSAT2 alarm bit 10 V(LDK2) < 1.0 V sets the LDKSAT2 alarm bit 11 V(LDK2) < 1.2 V sets the LDKSAT2 alarm bit Table 111: LDK saturation threshold selection chan- nel 2 REF2 Addr. 0x18/19; bit 9:0 R/W 0x000 0x000 Channel 2 regulator reference voltage set to minimum voltage . . . Channel 2 regulator reference voltage set to Vref = Vref0(1 + ∆ Vref (%) 100 )n+1, n from 0 to 1023 0x3FF Channel 2 regulator reference voltage set to maximum voltage Table 112: Regulator voltage reference channel 2 RACC1 Addr. 0x1A; bit 4 R/W 0 0 Current range high for channel 2 1 Current range low for channel 2 Table 113: Current range configuration channel 2 ADSNF2 Addr. 0x1A; bit 6 R/W 0 0 ADC measurement MDA2 pad (force) 1 ADC measurement PLR2 (sense) Table 114: ADC channel 2 sense/force selection |
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